FPV1006-125-R datasheet(32/41 Pages) VICOR

32 / 41 page

Cool-Power® ZVS Switching Regulators

Rev 2.5

Page 32 of 41

06/2017

PI33xx-x0

Functional Description

The PI33xx-x0 is a family of highly integrated ZVS-Buck regulators.

The PI33xx-x0 has a set output voltage that is trimmable within

a prescribed range shown in Table 1. Performance and maximum

output current are characterized with a specific external power

inductor (see Table 4).

For basic operation, Figure 58 shows the connections and

components required. No additional design or settings

are required.

ENABLE (EN)

EN is the enable pin of the converter. The EN Pin is referenced

to SGND and permits the user to turn the regulator on or off.

The EN default polarity is a positive logic assertion. If the EN pin

is left floating or asserted high, the converter output is enabled.

Pulling EN pin below 0.8VDC with respect to SGND will disable the

regulator output.

The EN input polarity can be programmed (PI33xx-20 device

versions only) via the I2C™ data bus. When the EN pin polarity is

programmed for negative logic assertion; and if the EN pin is left

floating, the regulator output is enabled. Pulling the EN pin above

1.0VDC with respect to SGND, will disable the regulator output.

Remote Sensing

An internal 100

Ω resistor is connected between REM pin and

VOUT pin to provide regulation when the REM connection is

broken. Referring to Figure 58, it is important to note that L1 and

COUT are the output filter and the local sense point for the power

supply output. As such, the REM pin should be connected at COUT

as the default local sense connection unless remote sensing to

compensate additional distribution losses in the system. The REM

pin should not be left floating.

Switching Frequency Synchronization

The SYNCI input allows the user to synchronize the controller

switching frequency by an external clock referenced to SGND.

The external clock can synchronize the unit between 50% and

110% of the preset switching frequency (fS). For PI33xx-20

device versions only, the phase delay can be programmed via I2C

bus with respect to the clock applied at SYNCI pin. Phase delay

allows PI33xx-20 regulators to be paralleled and operate in an

interleaving mode.

The PI33xx-x0 default for SYNCI is to sync with respect to the

falling edge of the applied clock providing 180° phase shift from

SYNCO. This allows for the paralleling of two PI33xx-x0 devices

without the need for further user programming or external sync

clock circuitry. The user can change the SYNCI polarity to sync

with the external clock rising edge via the I2C data bus (PI33xx-20

device versions only).

When using the internal oscillator, the SYNCO pin provides a

5V clock that can be used to sync other regulators. Therefore,

one PI33xx-x0 can act as the lead regulator and have additional

PI33xx-x0s running in parallel and interleaved.

Soft-Start

The PI33xx-x0 includes an internal soft-start capacitor to ramp the

output voltage in 2ms from 0V to full output voltage. Connecting

an external capacitor from the TRK pin to SGND will increase the

start-up ramp period. See, “Soft Start Adjustment and Track,” in

the Applications Description section for more details.

Output Voltage Trim

The PI33xx-x0 output voltage can be trimmed up from the preset

output by connecting a resistor from ADJ pin to SGND and can be

trimmed down by connecting a resistor from ADJ pin to VOUT. The

Table 1 defines the voltage ranges for the PI33xx-x0 family.

OUT

SYNCI

VS1

OUT

PGND

SYNCO

REM

TRK

ADJ

EAO

PI33xx

OUT

Table 1 — PI33xx-x0 family output voltage range

Figure 58 — ZVS-Buck with required components

Device

Output Voltage

Set

Range

PI3311-x0-LGIZ

1.0V

1.0 to 1.4V

PI3318-x0-LGIZ

1.8V

1.4 to 2.0V

PI3312-x0-LGIZ

2.5V

2.0 to 3.1V

PI3301-x0-LGIZ

3.3V

2.3 to 4.1V

PI3302-x0-LGIZ

5.0V

3.3 to 6.5V

PI3303-x0-LGIZ

12V

6.5 to 13.0V

PI3305-x0-LGIZ

15V

10.0 to 16.0V

FPV1006-125-R 数据表(PDF) 32 Page - Vicor Corporation

FPV1006-125-R 数据表(HTML) 32 Page - Vicor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

数据表下载