82C88

FN2979 Rev 3.00

Page 4 of 12

August 13, 2015

transfer. These two signals usually go to the chip select and

direction pins of a transceiver.

The MCE/PDEN pin changes function with the two modes of

the 82C88. When the 82C88 is in the IOB mode (IOB HIGH),

the PDEN signal serves as a dedicated data enable signal

for the I/O or Peripheral System bus.

Interrupt Acknowledge and MCE

The MCE signal is used during an interrupt acknowledge

cycle if the 82C88 is in the System Bus mode (IOB LOW).

During any interrupt sequence, there are two interrupt

acknowledge cycles that occur back to back. During the first

interrupt cycle no data or address transfers take place. Logic

should be provided to mask off MCE during this cycle. Just

before the second cycle begins the MCE signal gates a

master Priority Interrupt Controller’s (PIC) cascade address

onto the processor’s local bus where ALE (Address Latch

Enable) strobes it into the address latches. On the leading

edge of the second interrupt cycle, the addressed slave PIC

gates an interrupt vector onto the system data bus where it is

read by the processor.

If the system contains only one PIC, the MCE signal is not

used. In this case, the second Interrupt Acknowledge signal

gates the interrupt vector onto the processor bus.

Address Latch Enable and Halt

Address Latch Enable (ALE) occurs during each machine

cycle and serves to strobe the current address into the

82C82/82C83H address latches. ALE also serves to strobe

the status (S0, S1, S2) into a latch for halt state decoding.

Command Enable

The Command Enable (CEN) input acts as a command

qualifier for the 82C88. If the CEN pin is high, the 82C88

functions normally. If the CEN pin is pulled LOW, all

command lines are held in their inactive state (not three-

state). This feature can be used to implement memory

partitioning and to eliminate address conflicts between

system bus devices and resident bus devices.