ADC0803, ADC0804

FN3094 Rev 4.00

Page 11 of 17

August 2002

IC voltage regulators may be used for references if the ambient

temperature changes are not excessive.

Zero Error

The zero of the A/D does not require adjustment. If the minimum

can be done. The converter can be made to output 0000 0000

digital code for this minimum input voltage by biasing the A/D

utilizes the differential mode operation of the A/D.

The zero error of the A/D converter relates to the location of the

first riser of the transfer function and can be measured by

between the actual DC input voltage which is necessary to just

cause an output digital code transition from 0000 0000 to 0000

2.500V).

Full Scale Adjust

The full scale adjustment can be made by applying a

desired analog full scale voltage range and then adjusting the

which is just changing from 1111 1110 to 1111 1111. When

which is given by:

,

where:

are ground referenced.)

Clocking Option

The clock for the A/D can be derived from an external source

such as the CPU clock or an external RC network can be

added to provIde self-clocking. The CLK IN (pin 4) makes use

of a Schmitt trigger as shown in Figure 16.

Heavy capacitive or DC loading of the CLK R pin should be

avoided as this will disturb normal converter operation. Loads

less than 50pF, such as driving up to 7 A/D converter clock

inputs from a single CLK R pin of 1 converter, are allowed. For

larger clock line loading, a CMOS or low power TTL buffer or

PNP input logic should be used to minimize the loading on the

CLK R pin (do not use a standard TTL buffer).

Restart During a Conversion

If the A/D is restarted (CS and WR go low and return high)

during a conversion, the converter is reset and a new

conversion is started. The output data latch is not updated if

the conversion in progress is not completed. The data from the

previous conversion remain in this latch.

Continuous Conversions

In this application, the CS input is grounded and the WR input

is tied to the INTR output. This WR and INTR node should be

momentarily forced to logic low following a power-up cycle to

insure circuit operation. See Figure 17 for details.

Driving the Data Bus

This CMOS A/D, like MOS microprocessors and memories, will

require a bus driver when the total capacitance of the data bus

gets large. Other circuItry, which is tied to the data bus, will add

to the total capacitive loading, even in three-state (high-

impedance mode). Back plane busing also greatly adds to the

stray capacitance of the data bus.

There are some alternatives available to the designer to

handle this problem. Basically, the capacitive loading of the

data bus slows down the response time, even though DC

specifications are still met. For systems operating with a

relatively slow CPU clock frequency, more time is available in

which to establish proper logic levels on the bus and

therefore higher capacitive loads can be driven (see Typical

Performance Curves).

At higher CPU clock frequencies time can be extended for I/O

reads (and/or writes) by inserting wait states (8080) or using

clock-extending circuits (6800).

–



256

-----------------------------------------

–

=

CLK R

4

CLK IN

CLK

ADC0803-

ADC0804

19

R

C

1

1.1 RC

R

FIGURE 16. SELF-CLOCKING THE A/D

11

12

13

14

15

16

17

18

20

19

10

9

8

7

6

5

4

3

2

1

ADC0803 - ADC0804

WR

RD

CS

INTR

CLK IN

DGND

AGND

CLK R

V+

10K

10

F

+

DATA

START

ANALOG

INPUTS

150pF

OUTPUTS

N.O.

MSB

LSB

FIGURE 17. FREE-RUNNING CONNECTION