STM1001

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OPERATION

Reset Output

The

STM1001

MICROPROCESSOR

RESET

CIRCUIT asserts a reset signal to the MCU when-

70°C).

threshold an internal timer keeps RST low for the

returns high.

low. Each time RST is asserted, it stays low for at

below the reset threshold, the internal timer clears.

reset threshold. The active-low reset (RST) is an

open drain output.

The STM1001 is relatively immune to negative-go-

shows typical transient duration versus reset com-

parator overdrive (for which the STM1001 will

NOT generate a reset pulse). The graph was gen-

starting at 0.5V above the actual reset threshold

and ending below it by the magnitude indicated

(comparator overdrive). The graph indicates the

can have without causing a reset pulse. As the

magnitude of the transient increases (further be-

low the threshold), the maximum allowable pulse

width decreases. Any combination of duration and

overdrive which lies under the curve will NOT gen-

goes 100mV below the reset threshold and lasts

20µs or less will not cause a reset pulse. A 0.1µF

bypass capacitor mounted as close as possible to

er sinks current, but becomes an open circuit. In

most systems this is not a problem, as most MCUs

do not operate below 1V. However, in applications

where RST output must be valid down to 0V, a

pull-down resistor may be added to hold the RST

output low. This resistor must be large enough to

not load the RST output, and still be small enough

to pull the output to ground. A 100K

Ω resistor is

recommended.