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STSR30 数据表(PDF) 5 Page - STMicroelectronics |
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STSR30 数据表(HTML) 5 Page - STMicroelectronics |
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5 / 10 page ![]() STSR30 5/10 Figure 1 : TIMING DIAGRAM Figure 2 : STSR30 IN FLYBACK CONVERTER SECONDARY SIDE NOTES 1) Ceramic Capacitors C1 and C2 must be placed very close to the IC; 2) R1 andR2set theanticipationtimeby partitioning theVCC voltage; 3) R3 is a pull-up resistor; 4) R5 limits the current flowing through diode D2 when Freewheeling drain voltage is high; 5) D1 could be necessary to protect INHIBIT pin from negative voltages. 6) D2 could be necessary to protect INHIBIT pin from voltages higher than VCC 7) SGLGND layout trace must not include OUTGATE current paths. +5V Vo Vi +5V +5V Cout C2 100nF R1 R2 R5 TRANSFORMER MosfetN R3 D3 C1 100nF D1 D2 STSR30 8 1 3 7 Ck INHIBIT SGLGND SETANT PWM Feedback Loop option Low = OFF High = ON |
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