AD9621

REV. 0

–3–

ABSOLUTE MAXIMUM RATINGS

1

Supply Voltages (

±V

Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . .

±V

S

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V

Continuous Output Current

Operating Temperature Ranges

AN, AQ, AR . . . . . . . . . . . . . . . . . . . . . . . . –40

°C to +85°C

SQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55

°C to +125°C

Storage Temperature

Ceramic . . . . . . . . . . . . . . . . . . . . . . . . . . . –65

°C to +150°C

Plastic . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65

°C to +125°C

Junction Temperature

Ceramic

3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175

°C

Plastic

°C

Lead Soldering Temperature (1 minute)

4

. . . . . . . . . . +220

°C

NOTES

beyond which the serviceability of the circuit may be impaired. Functional

operability is not necessarily implied. Exposure to absolute maximum rating

conditions for an extended period of time may affect device reliability.

current should not be exceeded.

Ceramic DIP:

θ

Plastic SOIC:

θ

Plastic DIP:

θ

soldering. Throughhole devices (ceramic and plastic DIPs) can be soldered at

+300

°C for 10 seconds.

ORDERING GUIDE

Temperature

Package

Package

Model

Range

Description

Option

AD9621AN

–40

°C to +85°C

8-Pin Plastic DIP

N-8

AD9621AQ

–40

°C to +85°C

8-Pin Cerdip

Q-8

AD9621AR

–40

°C to +85°C

8-Pin SOIC

R-8

AD9621SQ

–55

°C to +125°C 8-Pin Cerdip

Q-8

EXPLANATION OF TEST LEVELS

Test Level

I

– 100% production tested.

II – 100% production tested at +25

°C, and sample tested at

specified temperatures. AC testing of “A” grade devices

done on sample basis.

III – Sample tested only.

IV – Parameter is guaranteed by design and characterization

testing.

V

– Parameter is a typical value only.

VI – All devices are 100% production tested at +25

°C. 100%

production tested at temperature extremes for extended

temperature devices; sample tested at temperature ex-

tremes for commercial/industrial devices.

–V

S

46.5mm

– INPUT

46.5mils

CB–

CB+

–INPUT +INPUT

+V

S

OUTPUT

54mils

Chip Layout

THEORY OF OPERATION

The AD9621 is a wide bandwidth, unity gain stable voltage

feedback amplifier. Since its open-loop frequency response fol-

lows the conventional 6 dB/octave roll-off, its gain bandwidth

product is basically constant. Increasing its closed-loop gain re-

sults in a corresponding decrease in small signal bandwidth. The

AD9621 typically maintains a 55 degree unity loop gain phase

margin. This high margin minimizes the effects of signal and

noise peaking.

Feedback Resistor Choice

At minimum stable gain (+1), the AD9621 provides optimum

occur due to lead (input, feedback) inductance and parasitic ca-

pacitance. For settling accuracy to 0.1% or less, this resistor

should not be required if layout guidelines are closely followed.

width, low parasitic peaking, and fast settling time.

When the AD9621 is used in the transimpedance (I-to-V)

peaking can be estimated as:

C

2

R

F

2

]

12

|

R

where

ω

pacitance at the inverting input. Typically

ω

RAD/sec (See Open Loop Frequency Response curve).

Ω and C

circuit capacitance). The bandwidth of the amplifier can be esti-

f

1.6

2

π R

For general voltage gain applications, the amplifier bandwidth

can be estimated as:

f

1

+

R

F

R

G









This estimation loses accuracy for gains approaching +2/–1 or

lower due to the amplifier’s damping factor. For these “low

gain” cases, the bandwidth will actually extend beyond the cal-

culated value. See Closed Loop BW plots.

R

NG

4

voltage gain applications, this should be the case.