82C52

FN2950 Rev 4.00

Page 5 of 21

November 25, 2015

Reset

During and after power-up, the 82C52 Reset Input (RST)

must be held high for at least two IX clock cycles in order to

initialize and drive the 82C52 circuits to an idle mode until

proper programming can be done. A high on RST causes

the following events to occur

• Resets the internal Baud Rate Generator (BRG) circuit

clock counters and bit counters. The Baud Rate Select

Register (BRSR) is not affected (except for bit 7 which is

reset to 0).

• Clears the UART Status Register (USR) except for

Transmission Complete (TC) and Transmit Buffer Register

Empty (TBRE) which are set. The Modem Control

Register (MCR) is also cleared. All of the discrete lines,

memory elements and miscellaneous logic associated

with these register bits are also cleared or turned off. Note

that the UART Control Register (UCR) is not affected.

Following removal of the reset condition (RST = low), the

82C52 remains in the idle mode until programmed to its

desired system configuration.

Programming The 82C52

The complete functional definition of the 82C52 is

programmed by the systems software. A set of control words

(UCR, BRSR and MCR) must be sent out by the CPU to

initialize the 82C52 to support the desired communication

format. These control words will program the character

length, number of stop bits, even/odd/no parity, baud rate,

etc. Once programmed, the 82C52 is ready to perform its

communication functions.

The control registers can be written to in any order. However,

the MCR should be written to last because it controls the

interrupt enables, modem control outputs and the receiver

enable bit. Once the 82C52 is programmed and operational,

these registers can be updated any time the 82C52 is not

immediately transmitting or receiving data.

Table 1. Shows the control signals required to access 82C52

internal registers.

UART Control Register (UCR)

The UCR is a write only register which configures the UART

transmitter and receiver circuits. Data bits D7 and D6 are not

used but should always be set to a logic zero (0) in order to

insure software compatibility with future product upgrades.

During the Echo Mode, the transmitter always repeats the

received word and parity, even when the UCR is

programmed with different or no parity. See Figure 1.

Baud Rate Select Register (BRSR)

The 82C52 is designed to operate with a single crystal or

external clock driving the IX input pin. The Baud Rate Select

Register is used to select the divide ratio (one of 72) for the

internal Baud Rate Generator circuitry. The internal circuitry

is separated into two separate counters, a Prescaler and a

Divisor Select. The Prescaler can be set to any one of four

division rates,

1, 3, 4, or 5.

TABLE 1.

CS0

A1

A0

WR

RD

OPERATION

00001

Data Bus

 Transmitter Buffer

Register (TBR)

00010

Receiver Buffer Register

(RBR)

 Data Bus

00101

Data Bus

 UART Control

Register (UCR)

00110

UART Status Register

(USR)

 Data Bus

01001

Data Bus

 Modem Control

Register (MCR)

01010

MCR

 Data Bus

01101

Data Bus

 Bit Rate Select

Register (BRSR)

01110

Modem Status Register

(MSR)

 Data Bus

D7 D6 D5 D4 D3 D2 D1 D0

Stop Bit

Select

0 = 1 Stop Bits

1 = 1.5 Stop Bits (Tx)

and 1 Stop Bit (Rx)

If 5 Data Bits Selected

1 = 2 Stop Bits for 6, 7

or 8 Data Bits Selected

Parity

Control

000 = Tx and Rx Even

001 = Tx and Rx Odd

010 = Tx Even, Rx

Odd

011 = Tx Odd, Rx

Even

100 = Tx Even, Rx

Check Disabled

101 = Tx Odd, Rx

Check Disabled

11X = Generation and

Check Disabled

Word

Length

Select

00 = 5 Bits

01 = 6 Bits

10 = 7 Bits

11 = 8 Bits

Reserved Set to 00 for Future

Product Upgrade

Compatibility

FIGURE 1. UCR