FN2974 Rev 4.00

Page 1 of 13

Sep 9, 2015

FN2974

Rev 4.00

Sep 9, 2015

82C84A

CMOS Clock Generator Driver

DATASHEET

The Intersil 82C84A is a high performance CMOS Clock

Generator-driver which is designed to service the requirements

of both CMOS and NMOS microprocessors such as the

80C86, 80C88, 8086 and the 8088. The chip contains a crystal

controlled oscillator, a divide-by-three counter and complete

“Ready” synchronization and reset logic.

Static CMOS circuit design permits operation with an external

frequency source from DC to 25MHz. Crystal controlled

operation to 25MHz is guaranteed with the use of a parallel,

fundamental mode crystal and two small load capacitors.

All inputs (except X1 and RES) are TTL compatible over

temperature and voltage ranges.

Power consumption is a fraction of that of the equivalent

bipolar circuits. This speed-power characteristic of CMOS

permits the designer to custom tailor his system design with

respect to power and/or speed requirements.

Features

• Generates the System Clock For CMOS or NMOS

Microprocessors

• Up to 25MHz Operation

• Uses a Parallel Mode Crystal Circuit or External

Frequency Source

• Provides Ready Synchronization

• Generates System Reset Output From Schmitt Trigger

Input

• TTL Compatible Inputs/Outputs

• Very Low Power Consumption

• Single 5V Power Supply

• Operating Temperature Ranges

- C82C84A . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

- I82C84A . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

- M82C84A . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

• Pb-Free Plus Anneal Available (RoHS Compliant)

Pinouts

82C84A

(PDIP, CERDIP)

TOP VIEW

82C84A (PLCC, CLCC)

TOP VIEW

10

11

12

13

14

15

16

17

18

9

8

7

6

5

4

3

2

1

X2

EFI

F/C

OSC

RES

X1

GND

ASYNC

RESET

CSYNC

PCLK

RDY1

READY

RDY2

CLK

AEN1

AEN2

4

5

6

7

8

910

11

12

13

3

2

1

20 19

15

14

18

17

16

RDY1

AEN2

NC

READY

RDY2

NC

F/C

EFI

X2

ASYNC

NO

LON

GE

R

AV

AI

LA

BL

E

OR

SU

PP

OR

TE

D