ISL91128

FN8732 Rev.3.00

Page 10 of 17

May 3, 2018

Buck-Boost Conversion Topology

The ISL91128 operates in either Buck or Boost mode. When

operating in conditions where PVIN is close to VOUT, the

ISL91128 alternates between Buck and Boost mode as

necessary to provide a regulated output voltage.

Figure 18 shows a simplified diagram of the internal switches

and external inductor.

PWM Operation

In Buck PWM mode, Switch D is continuously closed and

Switch C is continuously open. Switches A and B operate as a

synchronous buck converter when in this mode.

In Boost PWM mode, Switch A remains closed and Switch B

remains open. Switches C and D operate as a synchronous boost

converter when in this mode.

PFM Operation

During PFM operation in Buck mode, Switch D is continuously

closed, and Switch C is continuously open. Switches A and B

operate in Discontinuous mode during PFM operation. During

PFM operation in Boost mode, the ISL91128 closes Switch A and

Switch C to ramp up the current in the inductor. When the

inductor current reaches a certain threshold, the device turns off

Switches A and C, then turns on Switches B and D. With Switches

B and D closed, output voltage increases as the inductor current

ramps down.

In most operating conditions, there will be multiple PFM pulses

to charge up the output capacitor. These pulses continue until

decays to the lower threshold of the hysteretic PFM controller.

Switch B stays on after the multiple PFM pulses to hold LX1 to

GND, which reduces EMI noise (see Figure 8 on page 7).

When the output voltage is close to the input voltage, the

ISL91128 rapidly and smoothly switches from Boost to Buck

mode as needed to maintain the regulated output voltage. This

behavior provides excellent efficiency and very low output

voltage ripple.

The ISL91128 supports a bidirectional bus oriented protocol. The

protocol defines any device that sends data onto the bus as a

transmitter and the receiving device as the receiver. The device

controlling the transfer is the master and the device being

controlled is the slave. The master always initiates data transfers

and provides the clock for both transmit and receive operations.

Therefore, the ISL91128 operates as a slave device in all

applications. The SCL and SDA pins are open drain and need

external pull-up resistors connected with a proper voltage level,

interface is not used.

the MSB of each byte of data first.

Bypass Mode Operation

Bypass mode is always enabled and can be disabled by writing a

‘1’ to Bit 5 in the Mode Control register. When this function is

disabled, setting the EN pin to ‘0’ will disable the device. To

prevent the device from going into Bypass mode at power-up, EN

should be set to ‘1’ or connected to VIN before power is applied.

When the device enters Bypass mode, both high-side FETs are

turned ON, passing the input voltage to the output through the

two high-side FETs and the inductor. In Bypass mode, all other

blocks are turned off to minimize quiescent current

consumption. There should be at least 1ms of time delay

between entry into or exit out of Bypass mode, when

transitioning between Bypass mode and a Voltage Regulation

mode. Note there is no overcurrent protection in Bypass mode.

FIGURE 18. BUCK-BOOST TOPOLOGY

PVIN

VOUT

SWITCH A

SWITCH D

SWITCH B

SWITCH C

LX1

LX2