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AD8319ACPZ-R7 数据表(PDF) 15 Page - Analog Devices |
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AD8319ACPZ-R7 数据表(HTML) 15 Page - Analog Devices |
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15 / 19 page ![]() Data Sheet AD8319 Rev. D | Page 15 of 19 For the AGC loop to remain in equilibrium, the AD8319 must track the envelope of the output signal of the ADL5330 and provide the necessary voltage levels to the gain control input of the ADL5330. Figure 32 shows an oscilloscope screenshot of the AGC loop depicted in Figure 30. A 100 MHz sine wave with 50% AM modulation is applied to the ADL5330. The output signal from the VGA is a constant envelope sine wave with amplitude corresponding to a setpoint voltage at the AD8319 of 1.3 V. The gain control response of the AD8319 to the changing input envelope is also shown. CH1 200mV A Ch2 1.03V M2.00ms T 0.00000 s 1 Ch2 200mV AM MODULATED INPUT AD8319 OUTPUT Ch3 100mVΩ 2 3 ADL5330 OUTPUT Figure 32. Oscilloscope Screenshot Showing an AM Modulated Input Signal and the Response from the AD8319 Figure 33 shows the response of the AGC RF output to a pulse on VSET. As VSET decreases from 1.5 V to 0.4 V, the AGC loop responds with an RF burst. In this configuration, the input signal to the ADL5330 is a 1 GHz sine wave at a power level of −15 dBm. A Ch1 2.60V T 179.800µs AD8319 VSET PULSE ADL5330 OUTPUT 3 1 M10.µs Ch1 2.00V Ch3 50mVΩ T Figure 33. Oscilloscope Screenshot Showing the Response Time of the AGC Loop Response time and the amount of signal integration are controlled by CFLT. This functionality is analogous to the feedback capacitor around an integrating amplifier. While it is possible to use large capacitors for CFLT, in most applications, values under 1 nF provide sufficient filtering. Calibration in controller mode is similar to the method used in measurement mode. A simple two-point calibration can be done by applying two known VSET voltages or DAC codes and measuring the output power from the VGA. Slope and intercept can then be calculated by: Slope = (VSET1 − VSET2)/(POUT1 − POUT2) (8) Intercept = POUT1 − VSET1/Slope (9) VSETx = Slope × (POUTx − Intercept) (10) More information on the use of the ADL5330 in AGC applications can be found in the ADL5330 data sheet. OUTPUT FILTERING For applications in which maximum video bandwidth and, consequently, fast rise time are desired, it is essential that the CLPF pin be left unconnected and free of any stray capacitance. The nominal output video bandwidth of 50 MHz can be reduced by connecting a ground-referenced capacitor (CFLT) to the CLPF pin, as shown in Figure 34. This is generally done to reduce output ripple (at twice the input frequency for a symmetric input waveform such as sinusoidal signals). +4 VOUT CLPF AD8319 3.5pF ILOG CFLT 1.5kΩ Figure 34. Lowering the Postdemodulation Bandwidth CFLT is selected by pF 3.5 kΩ 1.5 2π 1 Bandwidth Video C FLT (11) The video bandwidth should typically be set to a frequency equal to approximately one-tenth the minimum input frequency. This ensures that the output ripple of the demodulated log output, which is at twice the input frequency, is well filtered. In many log amp applications, it may be necessary to lower the corner frequency of the postdemodulation filtering to achieve low output ripple while maintaining a rapid response time to changes in signal level. An example of a four-pole active filter is shown in the AD8307 data sheet. |
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