PLL500-17

Low Phase Noise VCXO (17MHz to 36MHz)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/29/05 Page 1

FEATURES

• VCXO output for the 17MHz to 36MHz range

• Low phase noise (-130 dBc @ 10kHz offset at

35.328MHz).

• CMOS output with OE tri-state control.

• 17 to 36MHz fundamental crystal input.

• Integrated high linearity variable capacitors.

• 12mA drive capability at TTL output.

• +/- 150 ppm pull range, max 5% linearity.

• Low jitter (RMS): 2.5ps period jitter.

• 2.5 to 3.3V operation.

• Available in 8-Pin SOIC, 6-pin SOT23 packages,

or DIE.

DESCRIPTION

The PLL500-17 is a low cost, high performance and

low phase noise VCXO for the 17 to 36MHz range,

providing less than -130dBc at 10kHz offset at

35.328MHz. The very low jitter (2.5 ps RMS period

jitter) makes this chip ideal for applications requiring

voltage controlled frequency sources. Input crystal

can range from 17 to 36MHz (fundamental resonant

mode).

FREQUENCY RANGE

MULTIPLIER

FREQUENCY

OUTPUT

BUFFER

No PLL

17 – 36 MHz

CMOS

BLOCK DIAGRAM

PIN CONFIGURATION

8-pin SOIC

6-pin SOT

XTAL

OSC

OE

XIN

XOUT

VCON

VARICAP

1

2

3

45

6

7

8

XIN

VDD*

VIN

GND

XOUT

VDD*

CLK

OE^

^: Denotes internal Pull-up

*: Only one VDD pin needs to be connected

1

2

3

5

6

OUT

GND

CLK

XIN

VDD

VIN

4