X9420

FN8195 Rev.1.00

Page 5 of 19

April 26, 2006

Figure 1. Detailed Potentiometer Block Diagram

Write in Process

The contents of the Data Registers are saved to

nonvolatile memory when the CS pin goes from LOW to

HIGH after a complete write sequence is received by the

device. The progress of this internal write operation can

be monitored by a Write In Process bit (WIP). The WIP bit

is read with a Read Status command.

INSTRUCTIONS

Address/Identification (ID) Byte

The first byte sent to the X9420 from the host, following

a CS going HIGH to LOW, is called the Address or

Identification byte. The most significant four bits of the

slave address are a device type identifier, for the X9420

this is fixed as 0101[B] (refer to Figure 2).

The least significant bit in the ID byte selects one of two

devices on the bus. The physical device address is

compares the serial data stream with the address input

state; a successful compare of the address bit is

required for the X9420 to successfully continue the

The remaining three bits in the ID byte must be set to 110.

Figure 2. Address/Identification Byte Format

Instruction Byte

The next byte sent to the X9420 contains the instruction

and register pointer information. The four most

significant bits are the instruction. The next two bits point

to one of four data registers. The format is shown below

in Figure 3.

Figure 3. Instruction Byte Format

The four high order bits of the instruction byte specify the

the four registers that is to be acted upon when a

register oriented instruction is issued. The last two bits

are defined as 0.

Serial Data Path

From Interface

Circuitry

Register 0

Register 1

REGISTER 2

REGISTER 3

Serial

Bus

Input

Parallel

Bus

Input

Counter

Register

INC/DEC

Logic

UP/DN

CLK

Modified SCK

UP/DN

8

6

C

O

U

N

T

E

R

D

E

C

O

D

E

Wiper

(WCR)

1

00

11

0A0

Device Type

Identifier

Device Address

1

I1

I2

I3

I0

R1

R0

0

0

Register

Select

Instructions