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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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X98021 数据表(PDF) 7 Page - Renesas Technology Corp |
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X98021 数据表(HTML) 7 Page - Renesas Technology Corp |
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7 / 29 page  X98021 FN8219 Rev 3.00 Page 7 of 29 March 8, 2006 t HSYNCin-to-HSout = 7.5ns + (PHASE/64 +10.5)*tPIXEL D 1 D 3 Programmable Width and Polarity Analog Video In P 1 P 2 P 3 P 4 P 5 P 6 P 7 P 8 P 0 P 9 D 0 R P/GP/BP[7:0] HS OUT P 10 P 11 P 12 D 2 The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the AFE’s output signals DATACLK R S/GS/BS[7:0] HSYNC IN FIGURE 5. 48 BIT OUTPUT MODE Programmable Width and Polarity Analog Video In P 1 P 2 P 3 P 4 P 5 P 6 P 7 P 8 P 0 P 9 HS OUT P 10 P 11 The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the AFE’s output signals DATACLK HSYNC IN D 0 R P/GP/BP[7:0] D 2 D 1 R S/GS/BS[7:0] t HSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL FIGURE 6. 48 BIT OUTPUT MODE, INTERLEAVED TIMING |
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