74AC299

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INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

TRUTH TABLE

* When one or both controls are high, the eight input/output terminals are the high impedance state: howewer sequential operation or cleaning

of the register is not affected.

Z : High Impedance

Qn0 : The level of An before the indicated steady state input conditions were established.

Qnn : The level of Qn before the most recent active transition indicated by OR

a, h : The level of the steadystate inputs A, H, respectively.

X : Don’t Care

PIN No

SYMBOL

NAME AND FUNCTION

1, 19

S0, S1

Mode Select Inputs

2, 3

G1, G2

3-State Output Enable Inputs (Active LOW)

7, 13, 6, 14, 5, 15, 4, 16

A/QA to H/QH

Parallel Data Inputs or 3-State Parallel Outputs (Bus Driver)

8, 17

QA’ to QH’

Serial Outputs (Standard Output)

9

CLEAR

Asynchronous Master Reset Input (Active LOW)

11

SR

Serial Data Shift Right Input

12

CLOCK

Clock Input (LOW to HIGH, Edge-triggered)

18

SL

Serial Data Shift Left Input

10

GND

Ground (0V)

20

Positive Supply Voltage

MODE

INPUTS

INPUTS/OUTPUTS

OUTPUTS

CLEAR

FUNCTION

SELECTED

OUTPUT

CONTROL

CLOCK

SERIAL

A/QA

H/QH

QA’

QH’

S1

S0

G1*G2*SL

SR

Z

L

H

H

X

XXX

X

Z

Z

L

L

CLEAR

L

L

X

L

L

X

X

X

LLLL

L

X

L

L

L

X

X

X

LLLL

HOLD

H

L

L

L

L

X

X

X

QA0

QH0

QA0

QH0

SHIFT

RIGHT

H

L

H

L

L

X

H

H

QGn

H

QGn

H

L

H

L

L

X

L

L

QGn

L

QGn

SHIFT

LEFT

H

H

L

L

L

H

X

QBnH

QBnH

H

H

L

L

L

L

X

QBnL

QBnL

LOAD

H

H

H

X

X

X

X

a

h

a

h