Data Sheet

AD8133

Rev. A | Page 13 of 17

THEORY OF OPERATION

Each differential driver in the AD8133 differs from a

conventional op amp in that it has two outputs whose voltages

move in opposite directions. Like an op amp, it relies on high

open-loop gain and negative feedback to force these outputs to

the desired voltages. The AD8133 drivers make it easy to

perform single-ended-to-differential conversion, common-

mode level shifting, and amplification of differential signals.

Previous differential drivers, both discrete and integrated

designs, have been based on using two independent amplifiers

and two independent feedback loops, one to control each of the

outputs. When these circuits are driven from a single-ended

source, the resulting outputs are typically not well balanced.

Achieving a balanced output has typically required exceptional

matching of the amplifiers and feedback networks.

DC common-mode level shifting has also been difficult with

previous differential drivers. Level shifting has required the use

of a third amplifier and feedback loop to control the output

common-mode level. Sometimes, the third amplifier has also

been used to attempt to correct an inherently unbalanced

circuit. Excellent performance over a wide frequency range has

proven difficult with this approach.

Each of the AD8133 drivers uses two feedback loops to

separately control the differential and common-mode output

voltages. The differential feedback, set by the internal resistors,

controls only the differential output voltage. The internal

common-mode feedback loop controls only the common-mode

output voltage. This architecture makes it easy to arbitrarily set

the output common-mode level by simply applying a voltage to

internal common-mode feedback, to equal the voltage applied to

The AD8133 architecture results in outputs that are highly

balanced over a wide frequency range without requiring

external components or adjustments. The common-mode

feedback loop forces the signal component of the output

common-mode voltage to be zeroed. The result is nearly

perfectly balanced differential outputs of identical amplitude

that are exactly 180° apart in phase.

DEFINITION OF TERMS

Differential Voltage

Differential voltage refers to the difference between two node

voltages that are balanced with respect to each other. For

example, in Figure 34 the output differential voltage (or

equivalently output differential mode voltage) is defined as

(

)

ON

OP

dm

OUT

V

V

V

−

=

,

Common-mode voltage refers to the average of two node

voltages with respect to a common reference. The output

common-mode voltage is defined as

2

)

(

,

ON

OP

cm

OUT

V

V

V

+

=

Output Balance

Output balance is a measure of how well the differential output

signals are matched in amplitude and how close they are to

exactly 180° apart in phase. Balance is most easily determined

by placing a well-matched resistor divider between the

differential output voltage nodes and comparing the magnitude

of the signal at the divider’s midpoint with the magnitude of the

differential signal. By this definition, output balance error is the

magnitude of the change in output common-mode voltage

divided by the magnitude of the change in output differential-

mode voltage in response to a differential input signal.

dm

OUT

cm

OUT

V

V

Error

Balance

Output

,

,

∆

∆

=

ANALYZING AN APPLICATION CIRCUIT

The AD8133 uses high open-loop gain and negative feedback to

force its differential and common-mode output voltages to

minimize the differential and common-mode input error

voltages. The differential input error voltage is defined as the

Figure 34. For most purposes, this voltage can be assumed to be

zero. Similarly, the difference between the actual output

be assumed to be zero. Starting from these two assumptions,

any application circuit can be analyzed.

CLOSED-LOOP GAIN

The differential mode gain of the circuit in Figure 34 can be

described by the following equation.

2

=

=

G

F

IN,dm

OUT,dm

R

R

V

V

+

–

Figure 34.