LTC6752/LTC6752-1/

LTC6752-2/LTC6752-3/

LTC6752-4

17

6752fc

For more information www.linear.com/LTC6752

applicaTions inForMaTion

Circuit Description

The block diagram is shown in Figure 1. There are dif-

for the output stage, an output pin (Q), a pin for latching

and adjusting hysteresis (LE/HYST), and a pin to put the

device in a low power mode (SHDN). In the LTC6752

and LTC6752-1, the two positive supply pins are bonded

of a rail-to-rail input stage, an intermediate gain stage,

and an output stage driving a pair of complementary FETs

capable of taking the output pin to either supply rail. A

Latching/Hysteresisinterfaceblockallowstheusertolatch

the output state and/or remove or adjust the comparator

input hysteresis. All of the internal signal paths make use

of low voltage swings for high speed at low power.

The LTC6752-3 has an additional inverted output stage

(not shown) for a complementary logic output signal.

Power Supply Configurations

The LTC6752-2/LTC6752-3/LTC6752-4 have separate

positive supply pins for the input and output stages that

allow for separate voltage ranges for the analog input,

and the output logic. Figure 2 shows a few possible con-

figurations. For reliable and proper operation, the input

supply pin should be between 2.45V and 5.25V above the

negative supply pin, and the output supply pin should be

between 1.71V and 3.5V above the negative supply pin.

There are no restrictions regarding the sequence in which

thesuppliesareapplied,aslongastheabsolute-maximum

ratings are not violated.

The LTC6752 and LTC6752-1 have only one positive sup-

ply pin. The supply voltage should be between 2.45V and

3.5V for proper and reliable operation.

Input Voltage Range and Offset

The LTC6752 family uses a rail-to-rail input stage that

consists of a pnp pair and an npn pair that are active over

different input common mode ranges. The pnp pair is ac-

– 1.5V (low common mode region of operation). The npn

Partial activation of both pairs occurs when one input is in

the low common mode region of operation and the other

input is in the high common mode region of operation, or

trimmed offsets as long as both inputs are completely

in the low or high common mode region of operation.

In the transition region, the offset voltage may increase.

Applications that require good DC precision should avoid

the transition region.

Input Bias Current

When both inputs are in the low common mode region,

the input bias current is negative, with current flowing

out of the input pins. When both inputs are in the high

common mode region, the input bias current is positive,

with current flowing into the input pins.

The input stage has been designed to accommodate

large differential input voltages without large increases

in input bias current. With one input at the positive input

supply rail and the other input at the negative supply rail,

the magnitude of the input bias currents at either pin is

typically less than 3.5μA.

Figure 2. Typical Power Supply Configurations (Applicable to the LTC6752-2/LTC6752-3/LTC6752-4)

–

+

3V

3V

6752 F02

Q

0V

(a) SINGLE SUPPLY

–IN

+IN

–

+

1.8V

5V

Q

0V

(b) OUTPUT SUPPLY < INPUT SUPPLY

–IN

+IN

–

+

3.5V

2.5V

Q

0V

(c) OUTPUT SUPPLY > INPUT SUPPLY

–IN

+IN

–

+

0V

2.5V

Q

–2.5V

(d) NEGATIVE OUTPUT LOGIC

–IN

+IN