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PDMB50W12 数据表(PDF) 2 Page - Kyocera Kinseki Corpotation |
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PDMB50W12 数据表(HTML) 2 Page - Kyocera Kinseki Corpotation |
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2 / 4 page ![]() Module at Tj=25 unless otherwise specified Characteristic Symbol Test Condition Min. Typ. Max. Unit Collector-Emitter Cut-Off Current ICES = 1200V, = 0V Gate-Emitter Lea ka ge Current IGES = ±20V, = 0V Collector-Emitter Saturation Voltage VCE(sat.) = 50A,V = 15V (chip level) Tj=25 Tj=125 Tj=150 ate-Emitter Threshold Voltage VGE(th.) = 10V, = 1.7mA I np ut C ap ac i t a n ce Cies = 25V, = 0V, = 1MH O ut p ut C ap a ci t a n ce Coes Reverse Transfer Capacitance es Gate Char g e Qg Vcc=600V, Ic=50A, VGE=-15 +15V Switching Time Rise Tim e tr VCC= IC= RG= VGE= Tj= 600V Ls=38nH 50A Inductive Load 15 ±15V 150 urn-on Delay Time td(on) all Tim e tf Turn-off Delay Time td(off) Peak F orward Volta ge F = 50A,VGE=0V (chip level) Tj=25 Tj=125 Tj=150 Reverse Recovery Time VCC= IC= RG= VGE= Tj= 600V Ls=38nH 50A Inductive Load 15 ±15V 150 I nt er na l Lea d Re si st anc e RCC’+EE’ 1 Main Terminal - Chip / Per 1 Arm Stray Inductance LSCE Main Terminal - Main Terminal H . . . Thermal R esi s tan c e th(j-c) Junct ion t o C a s e Per 1 Arm (Tc Thermal R esi s tan c e Rth(c-f) Cas e t o heat s i nk Per 1 Arm Paste=1W/(m ) |
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