M48T58 datasheet(9/27 Pages) STMICROELECTRONICS

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M48T58, M48T58Y

OPERATION MODES

As Figure 6, page 5 shows, the static memory ar-

ray and the quartz controlled clock oscillator of the

M48T58/Y are integrated on one silicon chip. The

two circuits are interconnected at the upper eight

memory locations to provide user accessible

BYTEWIDE™ clock information in the bytes with

addresses 1FF8h-1FFFh. The clock locations

contain the century, year, month, date, day, hour,

minute, and second in 24 hour BCD format (except

for the century). Corrections for 28, 29 (leap year -

valid until 2100), 30, and 31 day months are made

automatically. Byte 1FF8h is the clock control reg-

ister. This byte controls user access to the clock

information and also stores the clock calibration

setting.

The eight clock bytes are not the actual clock

counters themselves; they are memory locations

consisting of BiPORT™ READ/write memory

cells. The M48T58/Y includes a clock control cir-

cuit which updates the clock bytes with current in-

formation once per second. The information can

be accessed by the user in the same manner as

any other location in the static memory array.

The M48T58/Y also has its own Power-fail Detect

circuit. The control circuitry constantly monitors

the single 5V supply for an out-of-tolerance condi-

tion. When VCC is out of tolerance, the circuit write

protects the SRAM, providing a high degree of

data security in the midst of unpredictable system

operation brought on by low VCC.As VCC falls be-

low the Battery Back-up Switchover Voltage

(VSO), the control circuitry connects the battery

which maintains data and clock operation until val-

id power returns.

Table 6. Operating Modes

Note: X = VIH or VIL;VSO = Battery Back-up Switchover Voltage.

1. See Table 10, page 16 for details.

Mode

VCC

DQ0-DQ7

Power

Deselect

4.75 to 5.5V

4.5 to 5.5V

VIH

High Z

Standby

Deselect

VIL

High Z

Standby

WRITE

VIL

VIH

VIL

DIN

Active

READ

VIL

VIH

VIL

VIH

DOUT

Active

READ

VIL

VIH

High Z

Active

Deselect

VSO to VPFD (min)

(1)

High Z

CMOS Standby

Deselect

≤ VSO(1)

High Z

Battery Back-up Mode

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