MM82PC12VMSLASH883 datasheet(4/8 Pages) NSC

4 / 8 page

Propagation Delays

Figure 1 illustrates the calculations of a more useful propa-

gation delay The figure uses a 5V supply with a tolerance of

10% ambient temperature of a25 C and a load capaci-

tance of 100 pF The AC Characteristics table depicts tPD

at 5V 25 C equalling 25 ns Use the graph in

Figure 1 to get

the degradation multiple for 150 pF The number shown is

109 The adjusted propagation delay is therefore 25 c

109 or 27 ns

TLC5596 – 7

Including jig and probe capacitance

Output Test Circuit

for Propagation Delays

TLC5596 – 8

TLC5596 – 9

FIGURE 1 Normalized Typical Propagation Delay vs

Load Capacitance

Pin Descriptions

The following describes the function of all the MM82PC12

inputoutput pins Some of these descriptions reference in-

ternal circuits

INPUT SIGNALS

Device Select (DS1 DS2 When DS1 is low and DS2 is high

the device is selected The output buffers are enabled and

the service request flip-flop is asynchronously reset

(cleared) when the device is selected

Mode (MD)

When MD is high (output mode) the output

buffers are enabled and the source of the data latch clock

input is the device selection logic (DS1 DS2) When MD is

low (input mode) the state of the output buffers is deter-

mined by the device selection logic (DS1 DS2) and the

source of the data latch clock input is the strobe (STB) in-

put

Strobe (STB)

STB is used as the data latch clock input

when the mode (MD) input is low (input mode) STB is also

used to synchronously set the service request flip-flop

which is negative edge triggered

Data In (DI1–DI8) Data In is the 8-bit data input to the data

latch which consists of eight D-type flip-flops incorporating

a level sensitive clock While the data latch clock input is

high the Q output of each flip-flop follows the data input

When the clock input returns low the data latch stores the

data input Clear (CLR) is only effective when the clock is

low (latch in the latched state)

Clear (CLR)

When CLR is low the data latch is reset

(cleared) if the clock is also low The clock input high over-

rides the clear (CLR) input data latch reset CLR being low

also resets the service request flip-flop The service request

flip-flop is in the non-interrupting state when reset

OUTPUT SIGNALS

Interrupt (INT)

The interrupt pin goes low (interrupting

state) when either the service request flip-flop is synchro-

nously set by the strobe (STB) input or the device is select-

Data Out (DO1–DO8) Data Out is the 8-bit data output of

data buffers which are TRI-STATE non-inverting stages

These buffers have a common control line that either en-

ables the buffers to transmit the data from the data latch

outputs or disables the buffers by placing them in the high-

impedance state

Reliability Information

Gate Count 108

Transistor Count 248

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