ADCMP391 datasheet(13/17 Pages) AD

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Data Sheet

ADCMP391/ADCMP392/ADCMP393

Rev. D | Page 13 of 17

SEQ

OUTA

OUTB

OUTC

OUTD

Figure 33. Programmable Sequencing Control Circuit Timing Diagram

When the SEQ signal changes from low to high impedance, the

load capacitor, CL, starts to charge. The time it takes to charge the

load capacitor to the pull-up voltage (in this case, VREF or VCC) is the

maximum delay programmable in the circuit. It is recommended

to have the threshold within 10% to 90% of the pull-up voltage.

Calculate the maximum allowable delay by

tMAX = tR = 2.2 RPULLUP CL

(17)

The delay of each output is changed by changing the threshold

voltage, V1 to V4, when the comparator changes its output state.

To calculate the voltage thresholds for the comparator, use the

following formulas:













−

PULLUP

REF

(18)













−

PULLUPC

REF

(19)













−

PULLUPC

REF

(20)













−

PULLUP

REF

(21)

The threshold voltages can come from a voltage reference or a

voltage divider circuit, as shown in Figure 31.

First, determine the allowable current, IDIV, flowing through the

resistor divider. After the value for IDIV is determined, calculate

R1, R2, R3, R4, and R5 using the following formulas:

DIV

REF

DIV

(22)

REF

DIV

V1R

R1 =

(23)

V2R

REF

DIV

−

(24)

V3R

REF

DIV

−

(25)

V4R

REF

DIV

−

(26)

R5 = RDIV − R1 − R2 − R3 − R4

(27)

To create a mirrored voltage sequence, add a resistor, RMIRROR,

between the pull-up resistor (RPULLUP) and the load capacitor

(CL) as shown in Figure 34.

OUTD

INA+

INB+

INC+

IND+

INA–

INB–

INC–

IND–

OUTC

OUTB

OUTA

RPULLUP

RMIRROR

VREF/VCC

SEQ

Figure 34. Circuit Configuration for a Mirrored Voltage Sequencer

Figure 34 shows the circuit configuration for a mirrored voltage

sequencer. When SEQ changes from low to high impedance, the

response is similar to Figure 33. When SEQ changes from high

impedance to low, the load capacitor (CL) starts to discharge at a

rate set by RMIRROR. The delay of each comparator is dependent

on the threshold voltage previously set for t1 to t4. The result is a

mirrored power-down sequence.

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