AD8436

Data Sheet

Rev. E | Page 14 of 21

Crest factor performance is mostly applicable for unexpected

waveforms such as switching transients in switchmode power

supplies. In such applications, most of the energy is in these peaks

and can be destructive to the circuitry involved, although the

average ac value can be quite low.

Figure 14 shows the effects of an additional crest factor capacitor of

0.1 μF and an averaging capacitor of 10 μF. The larger capacitor

serves to average the energy over long spaces between pulses,

while the CCF capacitor charges and holds the energy within

the relatively narrow pulse.

Using the FET Input Buffer

The on-chip FET input buffer is an uncommitted FET input

op amp used for driving the 8 kΩ I-to-V input resistor of the

rms core. Pin IBUFOUT, Pin IBUFIN−, and Pin IBUFIN+ are

the input/output; Pin IBUFINGN is an optional connection for

gain in the input buffer; and Pin IBUFV+ connects power to the

buffer. Connecting Pin IBUFV+ to the positive rail is the only

power connection required because the negative rail is internally

connected. Because the input stage is a FET and the input

impedance must be very high to prevent loading of the source, a

large value (10 MΩ) resistor connects from midsupply at Pin IGND

to Pin IBUFIN+ to prevent the input gate from floating high.

For unity gain, connect the IBUFOUT pin to the IBUFIN− pin.

For a gain of 2×, connect the IBUFGN pin to ground. See Figure 9

and Figure 10 for large and small signal responses at the two

built-in gain options.

The offset voltage of the input buffer is ≤500 μV, depending on

grade. A capacitor connected between the buffer output pin

(IBUFOUT) and the RMS pin is recommended so that the

input buffer offset voltage does not contribute to the overall

error. Select the capacitor value for least minimum error at the

lowest operating frequency. Figure 33 is a schematic showing

internal components and pin connections.

IBUFOUT

IBUFIN+

IBUFIN–

–

+

IBUFGN

10kΩ

10kΩ

10pF

6

5

4

3

2

RMS

10µF

0.47µF

10MΩ

11

IGND

16

IBUFV+

Figure 33. Connecting the FET Input Buffer

Capacitor coupling at the input and output of the FET buffer is

recommended to avoid transferring the buffer offset voltage to

the output. Although the FET input impedance is extremely high,

the 10 MΩ centering resistor connected to IGND must be taken

into account when selecting an input capacitor value. This is simply

an impedance calculation using the lowest desired frequency, and

finding a capacitor value based on the least attenuation desired.

Because the 10 kΩ resistors are closely matched and trimmed to

a high tolerance, the input buffer gain can increase to several

hundred with an external resistor connected to Pin IBUFIN−.

The bandwidth diminishes at the typical rate of a decade per 20 dB

of gain, and the output voltage range is constrained. The small-

signal response, shown in Figure 9, serves as a guide. For example,

if detecting small input signals at power line frequencies, an

external 100 Ω resistor connected from IBUFIN− to ground sets

the gain to 101 and the 3 dB bandwidth to ~15 kHz, which is

adequate for amplifying power line frequencies.

Using the Output Buffer

The AD8436 output buffer is a precision op amp optimized for

high dc accuracy. Figure 34 shows a block diagram of the basic

amplifier and input/output pins. The amplifier often configures

as a unity gain follower but easily configures for gain, as a

Sallen-Key, low-pass filter (in conjunction with the built-in 16 kΩ

I-to-V resistor). Note that an additional 16 kΩ on-chip precision

resistor in series with the inverting input of the amplifier balances

output offset voltages resulting from the bias current from the

noninverting amplifier. The output buffer disconnects from

Pin OUT for precision core measurements.

As with the input FET buffer, the amplifier positive supply

disconnects when not needed. In normal circumstances, the

buffers connect to the same supply as the core. Figure 35 shows

the signal connections to the output buffer. Note that the input

offset voltage contribution by the bias currents are balanced by

equal value series resistors, resulting in near zero offset voltage.

OBUFOUT

OBUFIN+

OBUFIN–

16kΩ

OUTPUT BUFFER

–

+

Figure 34. Output Buffer Block Diagram

OUT

16kΩ

16kΩ

OGND

OBUFOUT

OBUFIN+

OBUFIN–

–

+

CORE

IBIAS

9

8

14

13

12

Figure 35. Basic Output Buffer Connections

For applications requiring ripple suppression in addition to the

single-pole output filter described previously, the output buffer

is configurable as a two-pole Sallen-Key filter using two external

resistors and two capacitors. At just over 100 kHz, the amplifier

has enough bandwidth to function as an active filter for low

frequencies such as power line ripple. For a modest savings in

cost and complexity, the external 16 kΩ feedback resistor can be