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ADCMP392ARZ 数据表(PDF) 14 Page - Analog Devices

部件名 ADCMP392ARZ
功能描述  Comparators
PDF  17 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADCMP392ARZ 数据表(HTML) 14 Page - Analog Devices

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ADCMP391/ADCMP392/ADCMP393
Data Sheet
Rev. D | Page 14 of 17
SEQ
VC
L
OUTA
OUTB
OUTC
OUTD
t4
t3
t2
t7
t8
t1
t5
t6
V1
V2
V3
V4
V4
V3
V2
V1
Figure 35. Mirrored Voltage Sequencer Timing Diagram
The timing diagram for the mirrored voltage sequencer is
shown in Figure 35.
Equation 18 through Equation 21 must account for the
additional resistance, RMIRROR, in the calculations of the voltage
thresholds. To calculate these new thresholds, see Equation 28
through Equation 31.
(
)


−
=
+
−
L
MIRROR
PULLUP
1
C
R
R
t
REF
e
V
V1
1
(28)
(
)
−
=
+
−
L
MIRROR
PULLUP
2
C
R
R
t
REF
e
V
V2
1
(29)
(
)


−
=
+
−
L
MIRROR
PULLUP
3
C
R
R
t
REF
e
V
V3
1
(30)
(
)


−
=
+
−
L
MIRROR
PULLUP
4
C
R
R
t
REF
e
V
V4
1
(31)
RMIRROR provides the mirrored delay by prolonging the discharge
time of the capacitor. The mirrored voltage sequencer uses the
same threshold in Equation 28 to Equation 31 in a decreasing
order. To calculate the exact value of the mirrored delay time,
see Equation 32 through Equation 35.
−
=
REF
L
MIRROR
5
V
V
C
R
t
4
ln
(32)
−
=
REF
L
MIRROR
6
V
V
C
R
t
3
ln
(33)
−
=
REF
L
MIRROR
7
V
V
C
R
t
2
ln
(34)
−
=
REF
L
MIRROR
8
V
V1
C
R
t
ln
(35)
MIRRORED VOLTAGE SEQUENCER EXAMPLE
To illustrate how the mirrored voltage sequencer works, see
Figure 32 and then consider a system that uses a VREF of 1 V and
requires a delay of 50 ms when SEQ changes from low to high
impedance, and between each regulator when turning on. These
considerations require a rise time of at least 200 ms for the pull-up
resistor (RPULLUP) and the load capacitor (CL). The sum of the
resistance of RMIRROR and RPULLUP must be large enough to charge the
capacitor longer than the minimum required delay. For a
symmetrical mirrored power-down sequence, the value of RMIRROR
must be much larger than RPULLUP. A 10 kΩ RPULLUP value limits the
pull-down current to 100 µA while giving a reasonable value for
RMIRROR. A typical 1 µF capacitor together with a 150 kΩ RMIRROR
value gives a value of
tMAX = 2.2((160 × 103) × (1 × 10−6)) = 351 ms
(36)
The threshold voltage required by each comparator is set by
Equation 28 to Equation 31. For example,
−
=
−
×
×
×
−
×
−
6
10
1
3
10
160
3
10
50
1 e
V
V1
REF
where V1 = 268.38 mV.
Therefore, V2 = 464.74 mV, V3 = 608.39 mV, and V4 =
713.5 mV.
Next, consider 10 µA as the maximum current (IDIV) flowing
through the resistor divider network. This current gives the total
resistance of the divider network (RDIV) and the individual
resistor values using Equation 22 to Equation 27, resulting in
the following:
•
RDIV = 100 kΩ
•
R1 = 26.84 kΩ ≈ 26.7 kΩ
•
R2 = 19.64 kΩ ≈ 19.6 kΩ
•
R3 = 14.37 kΩ ≈ 14.3 kΩ
•
R4 = 10.51 kΩ ≈ 10.5 kΩ
•
R5 = 28.65 kΩ ≈ 28.7 kΩ



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