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SSM4321 数据表(PDF) 7 Page - Analog Devices |
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SSM4321 数据表(HTML) 7 Page - Analog Devices |
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7 / 24 page ![]() Data Sheet SSM4321 Rev. 0 | Page 7 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TOP VIEW (BALL SIDE DOWN) Not to Scale 1 A B C D 2 3 4 BALL A1 INDICATOR OUT+ SENSE+ SENSE– SDATAO/ PDM_DATA PVDD GND IOVDD BCLK_TDM/ PDM_CLK/ LRCLK_I2S VREG GND IN+ IN– OUT– GAIN SLOT FSYNC_TDM/ BCLK_I2S Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description A1 OUT+ Noninverting Output. A2 OUT− Inverting Output. A3 PVDD Amplifier Power Supply. A4 VREG Internal LDO Regulator Output. B1 SENSE+ Current Sense Positive Input. B2 GAIN Gain Control Pin. B3, B4 GND Ground. C1 SENSE− Current Sense Negative Input. C2 SLOT TDM Slot Selection Input. C3 IOVDD Input/Output Digital Power Supply. C4 IN+ Noninverting Input. D1 SDATAO/PDM_DATA TDM Serial Data Output/PDM Data Output. D2 FSYNC_TDM/BCLK_I2S TDM Frame Synchronization Input/I2S Bit Clock Input. D3 BCLK_TDM/PDM_CLK/ LRCLK_I2S TDM Bit Clock Input/PDM Clock Input/I2S LRCLK Input. D4 IN− Inverting Input. |
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