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SSM3302ACPZ-R7 数据表(PDF) 17 Page - Analog Devices |
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SSM3302ACPZ-R7 数据表(HTML) 17 Page - Analog Devices |
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17 / 20 page ![]() Data Sheet SSM3302 Rev. A | Page 17 of 20 Because the mono mode uses output sense circuitry attached to the left channel outputs, run PCB traces directly from the speaker to the left channel outputs and then extend the PCB traces to the right channel outputs. OUTPUT MODULATION DESCRIPTION The SSM3302 uses three-level, Σ-Δ output modulation. Each output can swing from PGND to PVDD and vice versa. Ideally, when no input signal is present, the output differential voltage is 0 V because there is no need to generate a pulse. In a real-world situation, however, there are always noise sources present. Due to this constant presence of noise, a differential pulse is occasionally generated in response to this stimulus. A small amount of current flows into the inductive load when the differential pulse is generated. However, most of the time, the output differential voltage is 0 V. This feature ensures that the current flowing through the inductive load is small. When the user sends an input signal, an output pulse is generated to follow the input voltage. The differential pulse density is increased by raising the input signal level. Figure 39 depicts three- level, Σ-Δ output modulation with and without input stimulus. Figure 39. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus LAYOUT As output power increases, care must be taken to lay out PCB traces and wires properly among the amplifier, load, and power supply; a poor layout increases voltage drops, consequently decreasing efficiency. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. For lowest DCR and minimum inductance, ensure that track widths are at least 200 mil for every inch of length and use 1 oz. or 2 oz. copper. Use large traces for the power supply inputs and amplifier outputs. Proper grounding guidelines help to improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. To maintain high output swing and high peak output power, ensure that the PCB traces that connect the output pins to the load and supply pins are as wide as possible to maintain the minimum trace resistances. It is also recommended that a large ground plane be used for minimum impedances. In addition, good PCB layout isolates critical analog paths from sources of high interference. High frequency circuits (analog and digital) should be separated from low frequency circuits. Properly designed multilayer PCBs can reduce EMI emission and increase immunity to the RF field by a factor of 10 or more compared with double-sided boards. A multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted by signal crossover. If the system has separate ground planes for small signal and high power connections, there should be no overlap between these planes. Stitch the power plane to the SSM3302 exposed pad using multiple vias. Proper layout improves heat conduction into the board, allowing operation at larger output power levels without overtemperature issues. INPUT CAPACITOR SELECTION Input capacitors are required if the input signal is not biased within the recommended input dc common-mode voltage range, if high-pass filtering is needed, or if a single-ended source is used. If high-pass filtering is needed at the input, the input capacitor and the input resistor of the SSM3302 form a high-pass filter with a corner frequency determined by the following equation: fC = 1/(2π × RIN × CIN) The input capacitor can significantly affect the performance of the circuit. Failure to use input capacitors degrades the output offset of the amplifier. BOOTSTRAP CAPACITORS The output stage of the SSM3302 uses a high-side NMOS driver, rather than PMOS driver. To generate the gate drive voltage for the high-side NMOS driver, a bootstrap capacitor for each output terminal acts as a floating power supply for the switching cycle. Using 0.22 μF ceramic capacitors with a voltage rating of 35 V or greater is recommended. OUTPUT > 0V +5V 0V OUTR+/ OUTL+ +5V 0V OUTR–/ OUTL– +5V 0V VOUT OUTPUT < 0V +5V 0V OUTR+/ OUTL+ +5V 0V OUTR–/ OUTL– 0V –5V VOUT OUTPUT = 0V OUTR+/ OUTL+ +5V 0V +5V 0V OUTR–/ OUTL– +5V –5V 0V VOUT |
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