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SSM4321ACBZ-R7 数据表(PDF) 10 Page - Analog Devices |
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SSM4321ACBZ-R7 数据表(HTML) 10 Page - Analog Devices |
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10 / 24 page ![]() SSM4321 Data Sheet Rev. 0 | Page 10 of 24 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 2.5 5.0 4.0 4.5 3.5 3.0 SUPPLY VOLTAGE (V) NO LOAD RL = 4Ω RL = 8Ω Figure 15. Quiescent Current vs. PVDD Supply Voltage, ADC Sense Enabled 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 2.5 5.0 4.0 4.5 3.5 3.0 SUPPLY VOLTAGE (V) NO LOAD RL = 4Ω RL = 8Ω Figure 16. Quiescent Current vs. PVDD Supply Voltage, ADC Sense Disabled 2.0 1.5 1.0 0.5 0 2.5 5.0 4.0 4.5 3.5 3.0 SUPPLY VOLTAGE (V) THD + N = 1% THD + N = 10% RL = 8Ω + 33µH Figure 17. Maximum Output Power vs. PVDD Supply Voltage, RL = 8 Ω 3.0 2.5 2.0 1.0 1.5 0.5 0 2.5 5.0 4.0 4.5 3.5 3.0 SUPPLY VOLTAGE (V) THD + N = 1% THD + N = 10% RL = 4Ω + 15µH Figure 18. Maximum Output Power vs. PVDD Supply Voltage, RL = 4 Ω 4.0 3.5 3.0 2.5 2.0 1.0 1.5 0.5 0 2.5 5.0 4.0 4.5 3.5 3.0 SUPPLY VOLTAGE (V) THD + N = 1% THD + N = 10% RL = 3Ω + 7.5µH Figure 19. Maximum Output Power vs. PVDD Supply Voltage, RL = 3 Ω 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 3.0 1.5 2.0 2.5 1.0 0.5 OUTPUT POWER (W) RL = 8Ω + 33µH PVDD = 2.5V PVDD = 3.6V PVDD = 5.0V Figure 20. Supply Current vs. Output Power into 8 Ω |
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