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SC68C752B 数据表(PDF) 39 Page - NXP Semiconductors |
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SC68C752B 数据表(HTML) 39 Page - NXP Semiconductors |
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39 / 49 page ![]() SC68C752B_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 29 November 2005 39 of 49 Philips Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Fig 18. Receive timing D0 D1 D2 D3 D4 D5 D6 D7 active active 16 baud rate clock 002aab090 td11 next data Start bit Stop bit parity bit Start bit td10 RXA, RXB IRQ CS (read) data bits (0 to 7) 5 data bits 6 data bits 7 data bits Fig 19. Receive ready timing in non-FIFO mode D0 D1 D2 D3 D4 D5 D6 D7 002aab091 next data Start bit Stop bit parity bit td15 RXA, RXB RXRDYA, RXRDYB CS (read) active data ready Start bit data bits (0 to 7) active td16 |
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