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MP5034 数据表(PDF) 12 Page - Monolithic Power Systems |
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MP5034 数据表(HTML) 12 Page - Monolithic Power Systems |
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12 / 15 page ![]() MP5034 – USB CHARGING PORT CONTROLLER INTEGRATING QC 3.0 PROTOCOL MP5034 Rev 1.0 www.MonolithicPower.com 12 10/20/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. APPLICATION INFORMATION Selecting Input Capacitor Use low ESR capacitors for the best performance. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. A 22μF ceramic capacitor is recommended for most applications. When selecting the input capacitor, also consider the pre-stage converter stability. The input capacitor of the MP5034 is the output capacitor of the converter. Ensure that the converter is stable with additional output capacitors. Selecting VADJ Resistor ADJ has an internal, controlled, current sink. A QC mode transition can be achieved through ADJ. The ADJ sink current capability is 500 μA. For the pre-side converter, it is recommended to use a k Ω-level feedback resistor. Limit the current through the high-side feedback resistor below 500 μA (see Figure 5). There is another VADJ configuration value to limit the maximum output voltage and insert a resistor (R3) between FB and ADJ. With R3, the maximum output voltage can be limited with Equation (3): V V //R R //R R R V V FB 3 2 3 2 1 OUT_MAX (3) The required feedback resistor value of R1 must be greater than 30k Ω. IN ADJ MP5034 C1 Converter OUT FB R1 R2 R3 Figure 5: VADJ Set Maximum VOUT PCB Layout Guidelines Efficient PCB layout is critical for stable operation and thermal dissipation. For best results, refer to Figure 6 and follow the guidelines below. 1. Use short, direct, and wide traces to connect the IC’s IN pin. 2. Keep the ADJ trace to the upstream converter FB pin as short as possible and routed far from the switching node to prevent noise injection. DP DM ADJ EN IN IN GND NC FB DCDC VBUS GND DP DM GND IN C1 GND R3 Top Layer Bottom Layer Figure 6: Recommended Layout Design Example Table 2 is a design example following the application guidelines for the given specifications. Table 3: Design Example VIN (V) 3.6 - 12 Current (A) 3 The detailed application schematic is shown in Figure 7 through Figure 9. The typical performance and circuit waveforms are shown in the Typical Performance Characteristics section. For more detailed device applications, please refer to the related evaluation board datasheet. |
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