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THAT1240 数据表(PDF) 2 Page - List of Unclassifed Manufacturers |
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THAT1240 数据表(HTML) 2 Page - List of Unclassifed Manufacturers |
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2 / 8 page ![]() THAT Corporation; 45 Sumner Street; Milford, Massachusetts 01757-1656; USA Tel: +1 (508) 478-9200; Fax: +1 (508) 478-0990; Web: www.thatcorp.com Page 2 Balanced Line Receiver ICs Preliminary Information SPECIFICATIONS1 Absolute Maximum Ratings (T A = 25°C) Positive Supply Voltage (VCC) +18 V Power Dissipation (PD)(TA = 75°C) TBD mW Negative Supply Voltage (VEE) -18 V Operating Temperature Range (TOP) 0 to +70°C Storage Temperature Range (TST) -40 to +125°C Junction Temperature (TJ) 150°C Output Short-Circuit Duration (tSH) Continuous Lead Temperature (Soldering 60 seconds) TBD °C Positive Input Voltage (Ref, Sense) +18 V Negative Input Voltage (Ref, Sense) -18 V THAT1240 THAT1243 THAT1246 Positive Input Voltage (In+,In-) Vcc x 2 Vcc x 2.4 Vcc x 3 Negative Input Voltage (In+, In-) Vee x 2 Vee x 2.4 Vee x 3 Recommended Operating Conditions Parameter Symbol Conditions Min Typ Max Units Positive Supply Voltage VCC +2.2 +18 V Negative Supply Voltage VEE -2.2 -18 V Electrical Characteristics2 Parameter Symbol Conditions Min Typ Max Units Supply Current ICC No signal — 2.1 3.4 mA Input Voltage Range VIN-DIFF Differential (equal and opposite swing) THAT1240 (0 dB gain) — 21.5 — dBu 3 THAT1243 (-3 dB gain) — 24.5 — dBu THAT1246 (-6 dB gain) — 27.5 — dBu VIN-CM Common mode THAT1240 (0 dB gain) — 27.5 — dBu THAT1243 (-3 dB gain) — 29.1 — dBu THAT1246 (-6 dB gain) — 31.0 — dBu Input Impedance 4 ZIN-CM Common mode (all versions) — 9 — k W ZIN-DIFF Differential THAT1240 — 18 — k W THAT1243 — 21 — k W THAT1246 — 24 — k W Common Mode Rejection CMR Matched source impedances; VCM = ±10V DC 70 90 — dB 60 Hz 70 90 — dB 20 kHz — 85 — dB 44 kHz — 60 — dB Power Supply Rejection 5 PSR At 60 Hz, with VCC =-VEE THAT1240 — 82 — dB THAT1243 — 80 — dB 1. All specifications are subject to change without notice. 2. Unless otherwise noted, T A=25°C, VCC = +15V, VEE = -15V, Gain=-6dB 3. 0 dBu = 0.775Vrms. 4. See test circuit in Figure 2. 5. Defined with respect to differential gain. |
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