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TLE6365G 数据表(PDF) 9 Page - Infineon Technologies AG |
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TLE6365G 数据表(HTML) 9 Page - Infineon Technologies AG |
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9 / 17 page ![]() TLE 6365 Data Sheet Rev. 1.7 9 2003-06-02 2 Circuit Description Below some important sections of the TLE 6365 are described in more detail. Power On Reset In order to avoid any system failure, a sequence of several conditions has to be passed. In case of V CC power down (VCC < VRT for t > tRR) a logic LOW signal is generated at the pin RO to reset an external microcontroller. When the level of V CC reaches the reset threshold V RT, the signal at RO remains LOW for the Power-up reset delay time tRD before switching to HIGH. If V CC drops below the reset threshold VRT for a time extending the reset reaction time t RR, the reset circuit is activated and a power down sequence of period t RD is initiated. The reset reaction time tRR avoids wrong triggering caused by short “glitches” on the V CC-line. Figure 3 Reset Function ON Delay ON Delay invalid invalid ON Delay Start Up invalid t V CC RO H L V PG V RT t 1V typ.4,65V typ.4,70V t RD < t RR t RR < t RD t RD Power Sart-Up Normal Normal Failed N Failed started stopped |
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