CIRCUIT DESCRIPTION

STV7710/WAF

10/19

4.3

Description

STV7710/WAF includes all the logic and power circuits necessary to drive electrodes of a vacuum

fluorescent display (VFD). Binary values of each pixel of the displayed line are loaded into the shift

register DATA_A/B data bus. Data is shifted at each low to high transition of the CLK clock. After 96

shifts, the data is available at the output of the shift register. This output can be used to cascade

several Ics to drive higher resolution displays.

status is set according to the selected direction (refer to Table 6).

The maximum frequency of the shift clock is 40MHz.

When the STB signal is high, data are transferred from the shift register to the latch and power

output stages.

All the output data are kept memorized and held in the latch stage when the latch input STB is set

at low level.

Vsssub and Vsslog must be connected as close as possible to the logical reference ground of the

application. Also, make sure that TEST input pin is connected to ground (Figure 8).

STV7710/WAF is supplied with a 5 volt power supply. All the logic inputs can be driven either by 5V

CMOS logic, or by 3.3V CMOS logic.

Table 7: Shift register truth table

Input

Data-in / Data-out

Shift register function

F/R

CLK

DATA_A

DATA_B

H

↑

Data-in

Data-out

Forward shift

H

H or L

-

-

Steady

L

↑

Data-out

Data-in

Reverse shift

L

H or L

-

-

Steady

Table 8: Power output truth table

TEST

Qn

STB

BLK

POC

Driver Output

Comments

L

X

X

H

X

all “Low”

Output at low level

L

X

X

L

L

all “High”

Output at high level

L

X

L

L

H

Qn

Data latched

L

L

H

L

H

L

Data transfered

L

H

H

L

H

H

Data transfered