LTC6902

13

6902f

APPLICATIO S I FOR ATIO

using the simple equation below:

R

R

Spreading Percentage

MOD

SET

= 20 •

range and the spreading percentage range. The range of

ranging from 10k to 400k. The LTC6902 is tested and

specified for spreading of 10% and 40%. These are

practical limits that would apply to many systems but they

are not the actual limits of the part. The lower end limit is

set by internal offsets and mismatches. At lower spreading

percentages, these mismatches become more significant

and the error from the calculated, desired spreading

increases. A practical lower end limit would be about 5%

spreading. At the higher end internal mismatching be-

comes less significant, however other factors come into

proaching zero) cannot be reliably achieved. A practical

upper limit would be about 80% spreading.

To disable the SSFM, connect the MOD pin to ground.

Grounding the MOD pin disables the modulation and shuts

down the modulation circuitry. While leaving the MOD pin

is not a good method of disabling the modulation. The

open pin is susceptible to external noise coupling that can

affect the output frequency accuracy. Grounding the MOD

pin is the best way to disable the SSFM.

DRIVING LOGIC CIRCUITS

The outputs of the LTC6902 are suitable for driving

general digital logic circuits. The CMOS output drivers

have an ON resistance that is typically less than 100

Ω and

are very similar in performance to HCMOS logic outputs.

However, the form of frequency spreading used in the

LTC6902 may not be suitable for many logic designs.

Many logic designs have fairly tight timing and cycle-to-

cycle jitter requirements. These systems often benefit

from a spread spectrum clocking system where the fre-

quency is slowly and linearly modulated by a triangular

waveform, not a pseudorandom waveform. This type of

frequency spreading maintains a minimal difference in the

timing from one clock edge to the next adjacent clock edge

(cycle-to-cycle jitter). The LTC6902 uses a pseudorandom

modulating signal where the frequency transitions have

been slowed and the corners rounded by a 25kHz lowpass

filter. This filtered modulating signal may be acceptable for

many logic systems but the cycle-to-cycle jitter issues

must be considered carefully.

DRIVING SWITCHING REGULATORS

The LTC6902 is designed primarily to provide an accurate

and stable clock for switching regulator systems, espe-

cially those systems with multiple switching regulators

where all of the regulators are interleaved and are run at the

same frequency. This lowers the input capacitor require-

ments and prevents beat notes formed by mixing numer-

ous clock frequencies and their harmonics. The multiphase

outputs have CMOS drivers with an ON resistance that is

typically less than 100

Ω and are very similar in perfor-

mance to HCMOS logic outputs. This is suitable for

directly driving most switching regulators and switching

controllers. Linear Technology has a broad line of fully

integrated switching regulators and switching regulator

controllers designed for synchronization to an external

clock. All of these parts have one pin assigned for external

clock input. The nomenclature varies depending on the

part’s family history. SYNC, PLLIN, SYNC/MODE, SHDN,

EXTCLK, FCB and S/S (shorthand for SYNC/SHDN) are

examples of clock input pin names used with Linear

Technology ICs. The exact operating details depend on the

switching regulator in use, but generally switching is

synchronized to the rising edge of the clock. Since the

LTC6902’s master oscillator is passed through inverters

or flip-flops to generate its multiphase outputs, coincident

rising edges (or falling edges) cannot occur. This is true

even when the LTC6902 is used with a high percentage of

spreading.

For the best EMC performance, the LTC6902 should be

run with SSFM enabled and the master oscillator at its

highest frequency. The pseudorandom modulation signal