M69AR048B datasheet(4/29 Pages) STMICROELECTRONICS

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M69AR048B

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SUMMARY DESCRIPTION

The M69AR048B is a 32 Mbit (33,554,432 bit)

CMOS memory, organized as 2,097,152 words by

16 bits, and is supplied by a single 1.65V to 1.95V

supply voltage range.

M69AR048B is a member of STMicroelectronics

1T/1C (one transistor per cell) memory family.

These devices are manufactured using dynamic

random access memory cells, to minimize the cell

size, and maximize the amount of memory that

can be implemented in a given area.

However, through the use of internal control logic,

the device is fully static in its operation, requiring

no external clocks or timing strobes, and has a

standard Asynchronous SRAM Interface.

The internal control logic of the M69AR048B han-

dles the periodic refresh cycle, automatically, and

without user involvement.

Write cycles can be performed on a single Byte by

using Upper Byte Enable (UB) and Lower Byte En-

able (LB).

The device can be put into standby mode using

Chip Enable (E1) or in Power-Down mode by us-

ing Chip Enable (E2).

The device features several Power-Down modes,

making of power saving a user configurable op-

tion:

■

Partial Power-Down (4 Mbits, 8 Mbits or 16

Mbits) performs a limited refresh of the part of

the PSRAM array that contains essential data.

■

Deep Power-Down achieves a very low

current consumption by halting all the internal

activities. Since the refresh circuitry is halted,

the duration of the power-down should be less

than the maximum period for refresh.

Figure 2. Logic Diagram

Table 1. Signal Names

AI08154

A0-A20

DQ0-DQ15

VCC

M69AR048B

VSS

A0-A20

Address Input

DQ0-DQ15

Data Input/Output

E1, E2

Chip Enable, Power-Down

Output Enable

Write Enable

Upper Byte Enable

Lower Byte Enable

VCC

Supply Voltage

VSS

Ground

Not Connected

(no internal connection)

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