ST22N256 datasheet(1/8 Pages) STMICROELECTRONICS

部件名	ST22N256

功能描述	Smartcard 32-Bit RISC MCU with 256 Kbytes EEPROM Javacard HW Execution & Cryptographic Library

PDF	8 Pages

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制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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DATA BRIEF

June 2004

For further information contact your local ST sales office.

ST22N256

Smartcard 32-Bit RISC MCU with 256 Kbytes EEPROM

Javacard™ HW Execution & Cryptographic Library

8

PRODUCT FEATURES

I 32-BIT RISC CPU WITH 24-BIT LINEAR

MEMORY ADDRESSING

I 368 KBYTES USER ROM

I 16 KBYTES USER RAM

I 256K KBYTES USER EEPROM

32-BIT RISC CPU

I DUAL INSTRUCTION SET, JAVACARD™

AND NATIVE

I 4-STAGE PIPELINE

I 16 GENERAL PURPOSE 32-BIT REGISTERS,

AND SPECIAL REGISTERS

I 4 MASKABLE INTERRUPT LEVELS

I SUPERVISOR AND USER MODES

SECURITY

I CPU SECURITY INSTRUCTIONS

– DES and 3DES instructions

– Fast Multiply and Accumulate instructions for

Public Key and Elliptic Curve Cryptography

– CRC instruction

I RANDOM NUMBER GENERATOR

I EEPROM FLASH PROGRAMMING MODE

I CLOCK AND POWER MANAGEMENT

I VOLTAGE AND CLOCK FREQUENCY

SENSORS

I

ADVANCED MEMORY PROTECTION

– Memory Protection Unit for application

firewalling and peripheral access control

– Domain switching securely controlled by

protected Context Stack

– Native/Java, Code/Data memory attributes

with 128-byte granularity

I FOUR WORKING STACKS

– Java stack with both 16 and 32-bit accesses

– User and Supervisor mode stacks

– Security Context stack

Figure 1. Delivery Form

CRYPTOGRAPHIC LIBRARY

I ASYMMETRICAL ALGORITHMS

– Software Crypto libraries in separate ROM

area for efficient algorithm coding using a set

of advanced functions. RSA, signature/

verification.

– RSA key calculation including Prime number

generation SHA-1

I SYMMETRICAL ALGORITHMS

– DES, Triple DES, AES

CRYPTOGRAPHY PERFORMANCE

The following table provides the cryptographic

performances of the ST22N256 based on ST

Crypto Library.

Table 1. Preliminary Cryptographic

Performances

Algorithm

Function

Time(1)

1.

Internal clock at 33 MHz

RSA

1024 bits

Signature with CRT

79.0 ms

Signature without CRT(2)

2.

CRT: Chinese Reminder Theorem

242.0 ms

Verification (e=0x10001)

3.6 ms

RSA

2048 bits

Signature with CRT

485.0 ms

Signature without CRT

1.7 s

Verification (e=0x10001)

11.0 ms

DES

Triple

18 µs

Single

8 µs

SHA-1

512-bit Block

194 µs

AES-128

Encryption including subkey

computation

85 µs

Micromodule

Wafer

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