EVAL-ADAU1401EBZ datasheet(5/52 Pages) AD

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Data Sheet

ADAU1701

Rev. C | Page 5 of 52

SPECIFICATIONS

AVDD = 3.3 V, DVDD = 1.8 V, PVDD = 3.3 V, IOVDD = 3.3 V, master clock input = 12.288 MHz, unless otherwise noted.

ANALOG PERFORMANCE

Specifications are guaranteed at 25°C (ambient).

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ADC INPUTS

Number of Channels

Stereo input

Resolution

Bits

Full-Scale Input

100 (283)

µA rms (µA p-p)

2 V rms input with 20 kΩ (18 kΩ external + 2 kΩ

internal) series resistor

Signal-to-Noise Ratio

A-Weighted

100

Dynamic Range

−60 dB with respect to full-scale analog input

A-Weighted

100

Total Harmonic Distortion + Noise

−83

−3 dB with respect to full-scale analog input

Interchannel Gain Mismatch

250

mdB

Crosstalk

−82

Analog channel-to-channel crosstalk

DC Bias

1.4

1.5

1.6

Gain Error

−11

+11

DAC OUTPUTS

Number of Channels

Two stereo output channels

Resolution

Bits

Full-Scale Analog Output

0.9 (2.5)

V rms (V p-p)

Signal-to-Noise Ratio

A-Weighted

104

Dynamic Range

−60 dB with respect to full-scale analog output

A-Weighted

104

Total Harmonic Distortion + Noise

−90

−1 dB with respect to full-scale analog output

Crosstalk

−100

Analog channel-to-channel crosstalk

Interchannel Gain Mismatch

250

mdB

Gain Error

−10

+10

DC Bias

1.4

1.5

1.6

VOLTAGE REFERENCE

Absolute Voltage (CM)

1.4

1.5

1.6

AUXILIARY ADC

Full-Scale Analog Input

2.8

3.0

3.1

INL

0.5

LSB

DNL

1.0

LSB

Offset

Input Impedance

17.8

kΩ

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