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IN74ACT00 数据表(PDF) 2 Page - Integral Corp.

部件名 IN74ACT00
功能描述  Quad 2-Input NAND Gate High-Speed Silicon-Gate CMOS
PDF  4 Pages
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制造商  INTEGRAL [Integral Corp.]
网页  http://www.iksemi.com/
标志 INTEGRAL - Integral Corp.

IN74ACT00 数据表(HTML) 2 Page - Integral Corp.

  IN74ACT00 Datasheet HTML 1Page - Integral Corp. IN74ACT00 Datasheet HTML 2Page - Integral Corp. IN74ACT00 Datasheet HTML 3Page - Integral Corp. IN74ACT00 Datasheet HTML 4Page - Integral Corp.  
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IN74ACT00
8
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
VIN
DC Input Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
VOUT
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
±20
mA
IOUT
DC Output Sink/Source Current, per Pin
±50
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
Tstg
Storage Temperature
-65 to +150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
°C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/
°C from 65° to 125°C
SOIC Package: : - 7 mW/
°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
4.5
5.5
V
VIN, VOUT
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TJ
Junction Temperature (PDIP)
140
°C
TA
Operating Temperature, All Package Types
-40
+85
°C
IOH
Output Current - High
-24
mA
IOL
Output Current - Low
24
mA
tr, tf
Input Rise and Fall Time
*
(except Schmitt Inputs)
VCC =4.5 V
VCC =5.5 V
0
0
10
8.0
ns/V
* V
IN
from 0.8 V to 2.0 V
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND
≤(V
IN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.



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