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FST3257QSC 数据表(PDF) 6 Page - ON Semiconductor |
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FST3257QSC 数据表(HTML) 6 Page - ON Semiconductor |
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6 / 12 page ![]() © 1997 Fairchild Semiconductor Corporation www.fairchildsemi.com FST3257 • Rev. 1.0.3 5 AC Electrical Characteristics TA=-40 to +85°C, CL= 50pF, RU=RD=500 Ω VCC= 4.5 to 5.5V VCC=4.0V VCC=3.0 to 3.6V (7) Units Figure Symbol Parameter Conditions Min. Max. Min. Max. Min. Max. Propagation Delay Bus to Bus (6) 0.25 tPHL,tPLH Propagation Delay Select to Bus A (6) VIN=Open 0.25 0.25 1.0 6.8 ns Figure 3 Figure 4 Output Enable Time, Select to Bus B 1.0 7.9 tPZH,tPZL Output Enable Time, Select to Bus /OE VIN=7V for tPZL VIN=Open for tPZH 1.0 5.0 5.5 1.0 8.5 ns Figure 3 Figure 4 Output Disable Time, Select to Bus B 1.0 9.9 tPHZ,tPLZ Output Disable Time, Select to Bus /OE VIN=7V for tPLZ VIN=Open for tPHZ 1.5 5.3 5.6 1.5 9.9 ns Figure 3 Figure 4 Notes: 6. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical on resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance). 7. These parameters are guaranteed by design, but not tested. Capacitance TA=+25°C, f=1MHz. Capacitance is characterized by not tested. Symbol Parameter Conditions Typ. Max. Units CIN Control Pin Input Capacitance VCC=5.0V 3.0 pF A Port 7.0 B Port VCC /OE=5.0V 5.0 pF A Port 3.0 CI/O Input/Output Capacitance B Port VCC /OE=3.3V 3.5 pF |
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