© 2010 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FSA641 • Rev. 1.0.5

3

Pin Configuration

Figure 2. Functional Block Diagram

Figure 3. Pin Assignments (Top Through View)

Pin Descriptions

Pin #

Pin Name

Type

Description

20

CLKP

I/O

Common positive clock path

1

CLKN

I/O

Common negative clock path

2

D1P

I/O

Common positive data 1 path

3

D1N

I/O

Common negative data 1 path

4

D2P

I/O

Common positive data 2 path

5

D2N

I/O

Common negative data 2 path

15

CLKAP

I/O

A-port positive clock path

14

CLKAN

I/O

A-port negative clock path

13

DA1P

I/O

A-port positive data 1 path

12

DA1N

I/O

A-port negative data 1 path

11

DA2P

I/O

A-port positive data 2 path

10

DA2N

I/O

A-port negative data 2 path

18

CLKBP

I/O

B-port positive clock path

19

CLKBN

I/O

B-port negative clock path

16

DB1P

I/O

B-port positive data 1 path

17

DB1N

I/O

B-port negative data 1 path

6

/OE

Input

Output Enable (Active Low)

7

GND

Ground

Ground

8

VCC

Supply

Power; 0.1 µF decoupling capacitor to ground recommended

9

SEL

Input

A-port or B-port Select pin

0=A-port, 1= B-port

Paddle

n/a

NC

Not Connected

Truth Table

SEL

/OE

Function

Don’t Care

HIGH

Disconnect

LOW

LOW

D1, D2, CLK=DA1, DA2, CLKA

HIGH

LOW

D1, CLK=DB1, CLKB; D2 OPEN

D 2 P

D 2N

D 1 P

D 1N

C L K P

C L K N

S w itc h

C on tro l

C L KA P

C L KA N

DA 1 P

DA 1 N

DA 2 P

DA 2 N

C L KB P

C L KB N

DB 1 P

DB 1 N

F S A 64 1

G N D

/O E

SE L

0.1µF

1 0

9

8

7

6

1 1

1 2

1 3

1 4

1 5

5

4

3

2

1

1 6

1 7

1 8

1 9

2 0

D 2 N

D 2 P

D 1 N

D 1 P

C L K N

/O E

G N D

VC C

SE L

D A 2 N

D A 2 P

D A 1 N

D A 1 P

C L K A N

C L K A P

C L K P

C L KB N

C L KB P

DB 1 N

DB 1 P