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ADCLK905BCPZ-R7 数据表(PDF) 1 Page - Analog Devices |
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ADCLK905BCPZ-R7 数据表(HTML) 1 Page - Analog Devices |
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1 / 16 page  Ultrafast SiGe ECL Clock/Data Buffers Data Sheet ADCLK905/ADCLK907/ADCLK925 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2007–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES 95 ps propagation delay 7.5 GHz toggle rate 60 ps typical output rise/fall 60 fs random jitter (RJ) On-chip terminations at both input pins Extended industrial temperature range: −40°C to +125°C 2.5 V to 3.3 V power supply (VCC − VEE) APPLICATIONS Clock and data signal restoration and level shifting Automated test equipment (ATE) High speed instrumentation High speed line receivers Threshold detection Converter clocking GENERAL DESCRIPTION The ADCLK905 (one input, one output), ADCLK907 (dual one input, one output), and ADCLK925 (one input, two outputs) are ultrafast clock/data buffers fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. The ADCLK905/ADCLK907/ADCLK925 feature full-swing emitter coupled logic (ECL) output drivers. For PECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For NECL (negative ECL) operation, bias VCC to ground and VEE to the negative supply. The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate, 10 Gbps data rate, and 60 fs random jitter (RJ). The inputs have center tapped, 100 Ω, on-chip termination resistors. A VREF pin is available for biasing ac-coupled inputs. The ECL output stages are designed to directly drive 800 mV each side into 50 Ω terminated to VCC − 2 V for a total differential output swing of 1.6 V. The ADCLK905/ADCLK907/ADCLK925 are available in 16-lead LFCSP packages. TYPICAL APPLICATION CIRCUITS D D Q VCC VEE VT Q VREF Figure 1. ADCLK905 ECL 1:1 Clock/Data Buffer D1 D1 Q1 VCC VEE VT1 Q1 VREF1 D2 Q2 VCC VEE VT2 D2 VREF2 Q2 Figure 2. ADCLK907 ECL Dual 1:1 Clock/Data Buffer D D VCC VEE VT VREF Q1 Q1 Q2 Q2 Figure 3. ADCLK925 ECL 1:2 Clock/Data Fanout Buffer |
类似零件编号 - ADCLK905BCPZ-R7 |
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类似说明 - ADCLK905BCPZ-R7 |
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