ICS514

LOCO™ PLL CLOCK GENERATOR

CLOCK MULTIPLIER

IDT™ / ICS™ LOCO™ PLL CLOCK GENERATOR

2

ICS514

REV G 051310

Pin Assignment

Clock Decoding Table (MHz) with 14.31818

MHz Crystal or Clock Input

0 = connect directly to ground

1 = connect directly to VDD

M = leave unconnected (floating)

CLK and REF stop low in power-down state

Pin Descriptions

Notes:

1. With S1 = S0 = 0, the internal PLL is turned off and the CLK outputs stops low. The crystal oscillator and

REF output are still active.

2. With a clock input, the phase relationship between the input and the output clocks can change each time

the device is powered on. If a fixed phase relationship is required, use the ICS571 or other zero delay

multipliers.

X1/ I C L K

VD D

GN D

S1

RE F

S0

CL K

X2

1

2

3

4

8

7

6

5

8 - p i n ( 1 5 0 mil) S OIC

S1

S0

CLK

Multiplier

Accuracy

0

0

Power-down CLK

—

—

0

1

25

1.746

1 ppm

M

0

33.33

2.328

0.008%

M

1

40

2.794

1 ppm

1

0

50

3.492

1 ppm

1

1

66.66

4.656

0.008%

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

XI/ICLK

Input

Crystal connection to a 14.31818 MHz crystal or clock input.

2

VDD

Power

Connect to +3.3 V or +5 V.

3

GND

Power

Connect to ground.

4

REF

Output

Reference 14.31818 MHz crystal oscillator buffered clock output.

5

CLK

Output

Clock output per table above.

6

S0

Tri-level Input

Select 0 for output clock. Connect to GND or VDD or float. See

table above.

7

S1

Tri-level Input

Select 1 for output clock. Connect to GND or VDD or float. See

table above.

8

X2

Output

Crystal connection to a 14.31818 MHz crystal. Leave unconnected

for clock input.