©1994 Fairchild Semiconductor Corporation

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74LCX240 Rev. 1.6.0

January 2008

74LCX240

Low Voltage Octal Buffer/Line Driver with 5V Tolerant

Inputs and Outputs

Features

(1)

■

– Human body model > 2000V

– Machine model > 200V

Note:

1. To ensure the high-impedance state during power up

resistor: the minimum value or the resistor is

determined by the current-sourcing capability of the

driver.

General Description

The LCX240 is an inverting octal buffer and line driver

designed to be employed as a memory address driver,

clock driver and bus oriented transmitter or receiver. The

applications with capability of interfacing to a 5V signal

environment.

The LCX240 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation while maintain-

ing CMOS low power dissipation.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order

Number

Package

Number

Package Description

74LCX240WM

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74LCX240SJ

M20D

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LCX240MSA

MSA20

20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

74LCX240MTC

MTC20

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Implements proprietary noise/EMI reduction circuitry