MP6537 – 100V, THREE-PHASE, BLDC MOTOR PRE-DRIVER WITH PWM & ENABLE INPUTS

MP6537 Rev. 1.01

www.MonolithicPower.com

13

4/20/2018

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If the output is held at a high state for a long

period

of

time,

the

bootstrap

capacitor

discharges slowly. This eventually results in

gate driver loss for the HS-FET.

To prevent this, an internal charge pump

generates a voltage to maintain the bootstrap

capacitor charge.

The bootstrap voltage is monitored by an

under-voltage detection circuit. If any bootstrap

voltage falls below the VBST UVLO voltage, the

part initiates a new power-up sequence.

Dead-Time Adjustment

To prevent shoot through in any phase of the

bridge, it is necessary to have a dead time

the next complementary turn-on event. The

dead time for all three phases is set by a single

ground using Equation (3):

(3)

If DT is tied to GND directly, an internal

minimum dead time of 30ns is applied. Leave

DT open to generate a 6µs dead time.

VREG and VIN UVLO Protection

If at any time the voltage on VREG falls below

the VREG UVLO threshold voltage, the outputs

are

disabled,

and

the

nFAULT

signal

is

asserted. Operation resumes with a bootstrap

refresh when VREG rises above the UVLO

threshold.

If the voltage on VIN falls below the VIN UVLO

threshold voltage, all circuitry in the device is

disabled,

and

the

internal

logic

is

reset.

nFAULT is not asserted. Operation resumes

when VREG rises above the UVLO threshold.

Thermal Shutdown

If the die temperature exceeds safe limits, the

MP6537 enters a latched fault state similar to

an OCP event, and nFAULT is driven low. Only

nSLEEP or UVLO can unlatch the device from

an OTP fault lockout.