TABLE 23. Sequence of Transmitted Bytes

Control Register Definitions

OSD INTERFACE REGISTERS

Frame Control Register 1:

FRMCTRL1 (0x8400)

halftone

Fade

i/o

trans

clear

win2

win1

OSD

HTD

X

FEN

TD

CDPR

D2E

D1E

OsE

Bit 0

On-Screen Display Enable. The On-Screen Display will be disabled when this bit is a zero. When this bit is a one

the On-Screen Display will be enabled. This controls both Window 1 and Window 2.

Bit 1

Display Window 1 Enable. When this bit and Bit 0 of this register are both ones, Display Window 1 is enabled. If

either bit is a zero, then Display Window 1 will be disabled.

Bit 2

Display Window 2 Enable. When this bit and Bit 0 of this register are both ones, Display Window 2 is enabled. If

either bit is a zero, then Display Window 2 will be disabled.

Bit 3

Clear Display Page RAM. Writing a one to this bit will result in setting all of the Display Page RAM values to zero.

This bit is automatically cleared after the operation is complete. This bit is initially asserted by default at power up,

and will clear itself back to zero shortly after. Thus, the default value is one only momentarily, and then will remain

zero until manually asserted again or until the power is cycled.

Bit 4

Transparent Disable. When this bit is a zero, a palette color of black (i.e., color palette look-up table value of 0x00)

in the first 8 palette look-up table address locations (i.e., ATT0–ATT7) will be interpreted as transparent. When this

bit is a one, the color will be interpreted as black.

Bit 5

Fade In/Out Enable. When this bit is a 1, the OSD Fade In/Fade Out function is enabled. When this bit is a 0, the

function is disabled.

Bit 7

Half Tone Disable. When this bit is a 1, the OSD Half Tone Transparency function is disabled. When this bit is a 0,

the half tone transparency is enabled.

Frame Control Register 2:

FRMCTRL2 (0x8401)

Pixels per Line

Blink Period

PL[2:0]

BP[4:0]

Bits 4–0

Blinking Period. These five bits set the blinking period of the blinking feature, which is determined by mulitiplying

the value of these bits by 8, and then multiplying the result by the vertical field rate.

Bits 7–5

Pixels per Line. These three bits determine the number of pixels per line of OSD characters. See Table 24 which

gives the maximum horizontal scan rate. Also see Table 3 since the maximum recommended scan rate is also a

function of the PLLFREQRNG register, 0x843E[1:0].

TABLE 24. OSD Pixels per Line

Bits 7–5

Description

Max Horizontal Frequency (kHz)

0x0

704 pixels per line

110

0x1

768 pixels per line

110

0x2

832 pixels per line

110

0x3

896 pixels per line

110

0x4

960 pixels per line

110

0x5

1024 pixels per line

108

0x6

1088 pixels per line

102

0x7

1152 pixels per line

96

www.national.com

32