STV3500

2/3

DESCRIPTION

This integrated circuit (IC) is dedicated to low-cost

100-Hz TV chassis. Combined with a digital multi-

standard video decoder (STV2310) delivering an

ITU-R BT.601/656 video stream and a 2H video

scan IC, it provides a cost-effective, high-perfor-

mance solution for 2H applications. The STV3500

includes a field or line up-converter, a 32-bit ST20

CPU core with all peripherals required for control-

ling the TV chassis. Teletext data is extracted from

the incoming stream and decoded by the CPU. An

embedded On-Screen Display (OSD) generator

delivers the text and graphics. The Video Display

Pipeline performs feature box image processing

such as picture improvement, horizontal and verti-

cal rescaling and Temporal Noise Reduction.

The chip operates with a single external SDRAM

that is used for the field-rate up-conversion and

text

and

graphic

generations.The

external

SDRAM can be configured as a single bank of 16/

64/128 Mb (16-bit configuration) or a dual bank of

16 to 256 Mb (32-bit configuration). Application

program codes are stored in an external Flash

memory and executed from the SDRAM.

The STV3500 is designed using an 0.18 micron

CMOS process and delivered in a 160-pin PQFP

(0.65 mm pitch) package.

The ST3500 completes the Digital IC Core family

(STi5xxx, STi7xxx) which offers common CPU and

software platforms based on STMicroelectronics’

32-bit ST20 CPU core.

Table 1. Order Codes

Figure 1. Top Level Diagram

Part Number

Description

STV3500

Device in low-cost 0.65 mm pitch

PQFP 160 package

Build-Up

YSI

Video

ST20 Core

H100

PR_R

Y_G

PB_B

SDRAM

SDIN

TNR

HV Filter

8

YCRCB[7:0]

CLK_DATA

CTI

HSYNC

VSYNC

16/32

TV Peripherals

30

I/Os

Flash

Counter

NRESET

Triple

Clock

Generator

2D

Block Move

OSD

Pipeline

Pipeline

Block

Time Base

Generator

TV Chassis Control

CSA

Picture

Comp.

Cursor

BG

Plane

EMI4

Compositor

DAC

V100

27 MHz

Crystal