ICS511

LOCO™ PLL CLOCK MULTIPLIER

CLOCK MULTIPLIER

IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER

3

ICS511

REV K 051310

External Components

Decoupling Capacitor

As with any high-performance mixed-signal IC, the

ICS511 must be isolated from system power supply

noise to perform optimally.

A decoupling capacitor of 0.01µF must be connected

between VDD and the GND. It must be connected close

to the ICS511 to minimize lead inductance. No external

power supply filtering is required for the ICS511.

Series Termination Resistor

A 33Ω terminating resistor can be used next to the CLK

pin for trace lengths over one inch.

Crystal Load Capacitors

The total on-chip capacitance is approximately 12 pF. A

parallel resonant, fundamental mode crystal should be

used. The device crystal connections should include

pads for small capacitors from X1 to ground and from

X2 to ground. These capacitors are used to adjust the

stray capacitance of the board to match the nominally

required crystal load capacitance. Because load

capacitance can only be increased in this trimming

process, it is important to keep stray capacitance to a

minimum by using very short PCB traces (and no vias)

between the crystal and device. Crystal capacitors, if

needed, must be connected from each of the pins X1

and X2 to ground.

in pF. Example: For a crystal with a 16 pF load

capacitance, each crystal capacitor would be 8 pF

[(16-12) x 2] = 8.

6

S0

Tri-level Input

Select 0 for output clock. Connect to GND or VDD or float.

7

OE

Input

Output enable. Tri-states CLK output when low. Internal pull-up

resistor.

8

X2

Output

Crystal connection. Leave unconnected for clock input.

Pin

Number

Pin

Name

Pin

Type

Pin Description