UL22L-SH2-R datasheet(7/13 Pages) UTC

7 / 13 page

UL22

Preliminary

CMOS IC

UNISONICTECHNOLOGIESCO.,LTD

7 of 13

www.unisonic.com.tw

QW-R125-088.a



FUNCTIONAL DESCRIPTION (Cont.)

Refer to the dimming flowchart in Figure 3 and a reference design circuit in Figure 4. When AC input voltage is

applied to the LED Driver, the controller will be activated and started switching operation when the VDD voltage

exceeds 15.0V. The first-string of LEDs for example, Cool-White is activated by Q2 (SW1 signal). Its current is

detected by resistors R10 and R17. The detected voltage is compared with an internal reference then controller

outputs DRV duty signal with appropriate turn-on time. This regulates the LEDs current to the current setting level.

While Q2 (SW1) is initially turned on, the switch Q3 (SW2) is turned OFF. As the AC input voltage is removed

(wall switch turned off), both the VDD and CLK pin voltage decrease. Once CLK signal falls below its OFF threshold

of approximately 1.0V, the internal timer activates. If the 19ms (milli-second) period is completed before VDD drops

below 9.5V, Q2 will be turned off and Q3 will be turned on when AC input is re-applied with VDD exceeds 15.0V.The

current flowing through the second-string of LEDs follows the same current setting.

Note that the DRV output will be turned off once the19ms period is completed. During 19ms period, VDD pin level

must be held and kept above OFF threshold for proper control.

Similarly, if the controller is subjected to another OFF-ON action of the AC power as described above, Q2 will be

turned on while Q3 is OFF. The SW1 and SW2 can therefore select the LED channel to provide a light control.

If the AC input is re-applied after the VDD voltage drops below 4.0V, the controller and COLOR control temporal

circuit is reset. In this case, the circuit will result in Q2 being turned ON while Q3 is OFF; same as mentioned in the

initial AC power ON condition.

Gate Driver

The totem-pole DRV output delivers the gate-drive signal to the external power MOSFET. A proprietary

soft-clamp technique limits the output driver at 19.5V maximum. It is used to protect the external power MOSFET

from being over stressed.

Both SW1 and SW2 outputs deliver the gate-drive signals to the external MOSFETs for 2-channel LED color

control. The gate clamping voltage is 19.5V maximum.

Leading-Edge Blanking Time

In applications, when MOSFET Q1 is switched on, a current spike may occur at CS pin due to parasitic

components in the circuit. The controller employs a built-in filter to ignore the initial 750ns period of each switching

cycle at CS signal to avoid the MOSFET being turned off inadvertently.

UL22L-SH2-R 数据表(PDF) 7 Page - Unisonic Technologies

UL22L-SH2-R 数据表(HTML) 7 Page - Unisonic Technologies

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13

数据表下载