AD9736BBC datasheet(45/72 Pages) AD

45 / 72 page

Data Sheet

AD9734/AD9735/AD9736

Rev. B | Page 45 of 72

AD973x BIST PROCEDURE

Set RESET pin = 1.

Set input DATA = 0x0000 for unsigned (0x2000 for twos

complement).

Enable DATACLK_IN if it is not already running.

Run for at least 16 DATACLK_IN cycles.

Set RESET pin = 0.

Run for at least 16 DATACLK_IN cycles.

Set RESET pin = 1.

Run for at least 16 DATACLK_IN cycles.

Set RESET pin = 0.

10.

Set desired operating mode (1× mode and signed data are

default values and expected for the supplied BIST

vectors).

11.

Set CLEAR (Reg. 17, Bit 0), SYNC_EN (Reg. 17, Bit 1),

and LVDS_EN (Reg. 17, Bit 2) high.

12.

Wait 50 DATACLK_IN cycles to allow 0s to propagate

through and clear sync signatures.

13.

Set CLEAR low.

14.

Read all signature registers (Reg. 21, Reg. 20, Reg. 19, and

Reg. 18) for each of the four SEL (Reg. 17, Bits 7:6) values

and verify they are all 0x00.

LVDS Phase 1

a. Reg. 17 set to 0x26 (SEL1 = 0, SEL0 = 0,

SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).

b. Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.

LVDS Phase 2

a. Reg. 17 set to 0x66 (SEL1= 0, SEL0 = 1,

SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).

b. Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.

SYNC Phase 1

a. Reg. 17 set to 0xA6 (SEL1= 1, SEL0 = 0,

SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).

b. Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.

SYNC Phase 2

a. Reg. 17 set to 0xE6 (SEL1= 1, SEL0 = 1,

SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).

b. Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.

15.

Clock the BIST vector into the AD973x.

16.

After the BIST vector is clocked into the part, hold DATA =

0x0000 for unsigned (0x2000 for twos complement);

otherwise, the additional nonzero data changes the

signature.

17.

Read all signature registers (Reg. 21, Reg. 20, Reg. 19, and

Reg. 18, as described in Step 14 ) for each of the four SEL

(Reg. 17, Bits 7:6) values, and verify that they match the

expected signatures shown in Table 25.

18.

Flush the BIST circuitry. This must be done once before

valid data can be read. Loop back to Step 11 and rerun the

test to obtain the correct result.

19.

Each time BIST mode is entered, this flush needs to be

performed once. Multiple BIST runs can be performed

without reflushing as long as the device remains in BIST

mode.

AD973x EXPECTED BIST SIGNATURES

The BIST vectors provided on the AD973x-EB CD are in signed

mode, so no programming is necessary for the part to pass the

BIST. The BIST vector is for 1×, no FIFO, and signed data.

For testing all 14 input bits, use the vector all_bits_unsnew.txt

and verify against the signatures in Table 25.

Table 25. Expected BIST Data Readback for All Bits

LVDS Phase 1

LVDS Phase 2

SYNC Phase 1

SYNC Phase 2

CF71487C

66DF5250

CF71487C

66DF5250

For individual bit tests, use the vectors named bitn.txt (where n

is the desired bit number being tested) and compare them

against the values in Table 26.

Table 26. Expected BIST Data Readback for Individual Bits

Vector

Bit

Number

LVDS Rise

Expected

LVDS Fall

Expected

bit0.txt

AABF0A00

2A400500

bit1.txt

2BBF0A00

6B400500

bit2.txt

29BE0A00

E9400500

bit3.txt

2DBC0A00

ED410500

bit4.txt

25B80A00

E5430500

bit5.txt

35B00A00

F5470500

bit6.txt

15A00A00

D54F0500

bit7.txt

55800A00

955F0500

bit8.txt

D5C00A00

157F0500

bit9.txt

D5410A00

153E0500

bit10.txt

D5430B00

15BC0500

bit11.txt

D5470900

15B80400

bit12.txt

D54F0D00

15B00600

bit13.txt

D55F0500

15A00200

Note the following for Table 26:

•

The term rise refers to Phase 1 and fall refers to Phase 2.

•

Byte order is Decimal Register Address 21, Address 20,

Address 19, and Address 18.

•

SYNC phase should always equal LVDS phase in 1× mode.

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