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AD9739ABBCZ 数据表(PDF) 1 Page - Analog Devices |
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AD9739ABBCZ 数据表(HTML) 1 Page - Analog Devices |
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1 / 64 page  11-/14-Bit, 2.5 GSPS, RF Digital-to-Analog Converters Data Sheet AD9737A/AD9739A Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Direct RF synthesis at 2.5 GSPS update rate DC to 1.25 GHz in baseband mode 1.25 GHz to 3.0 GHz in mix-mode Industry leading single/multicarrier IF or RF synthesis Dual-port LVDS data interface Up to 1.25 GSPS operation Source synchronous DDR clocking Pin compatible with the AD9739 Programmable output current: 8.7 mA to 31.7 mA Low power: 1.1 W at 2.5 GSPS APPLICATIONS Broadband communications systems DOCSIS CMTS systems Military jammers Instrumentation, automatic test equipment Radar, avionics FUNCTIONAL BLOCK DIAGRAM DCI SDO SDIO SCLK CS DACCLK DCO CLK DISTRIBUTION (DIV-BY-4) SPI RESET DLL (MU CONTROLLER) IOUTN IOUTP VREF I120 IRQ 1.2V DAC BIAS AD9737A/AD9739A TxDAC CORE Figure 1. GENERAL DESCRIPTION The AD9737A/AD9739A are 11-bit and 14-bit, 2.5 GSPS high performance RF DACs that are capable of synthesizing wideband signals from dc up to 3 GHz. The AD9737A/AD9739A are pin and functionally compatible with the AD9739 with the exception that the AD9737A/AD9739A do not support synchronization or RZ mode, and are specified to operate between 1.6 GSPS and 2.5 GSPS. By elimination of the synchronization circuitry, some nonideal artifacts such as images and discrete clock spurs remain stationary on the AD9737A/AD9739A between power-up cycles, thus allowing for possible system calibration. AC linearity and noise performance remain the same between the AD9739 and the AD9737A/AD9739A. The inclusion of on-chip controllers simplifies system integration. A dual-port, source synchronous, LVDS interface simplifies the digital interface with existing FGPA/ASIC technology. On-chip controllers are used to manage external and internal clock domain variations over temperature to ensure reliable data transfer from the host to the DAC core. A serial peripheral interface (SPI) is used for device configuration as well as readback of status registers. The AD9737A/AD9739A are manufactured on a 0.18 µm CMOS process and operate from 1.8 V and 3.3 V supplies. They are supplied in a 160-ball chip scale ball grid array for reduced package parasitics. PRODUCT HIGHLIGHTS 1. Ability to synthesize high quality wideband signals with bandwidths of up to 1.25 GHz in the first or second Nyquist zone. 2. A proprietary quad-switch DAC architecture provides exceptional ac linearity performance while enabling mix- mode operation. 3. A dual-port, double data rate, LVDS interface supports the maximum conversion rate of 2500 MSPS. 4. On-chip controllers manage external and internal clock domain skews. 5. Programmable differential current output with an 8.66 mA to 31.66 mA range. |
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