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LTC2000

2000fb

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Setting the Full-Scale Current

The full-scale DAC output current (IOUTFS) is nominally

40mA, but can be adjusted as low as 10mA or as high as

60mA. The full-scale current is set by placing an external

resistor (RFSADJ) between the FSADJ pin and GND. An

internal reference control loop amplifier sets the current

flowing through RFSADJ such that the voltage at FSADJ

is equal to the voltage at REFIO, which is typically 1.25V.

IOUTFS is set as a scaled replica of the current flowing out

of the FSADJ pin (IFSADJ):

IFSADJ =

VREFIO

RFSADJ

IOUTFS = 16 •IFSADJ •

256

256 +GAIN _ ADJ

where GAIN_ADJ is a 6-bit two’s complement number

from –32 to 31 (nominally 0) which can be programmed

using SPI register 0x09 as shown in Table 2. For example,

for RFSADJ = 500Ω, VREFIO = 1.25V, and GAIN_ADJ =

0x00, the control loop will force 1.25V at the FSADJ pin,

causing 2.5mA to flow through RFSADJ. IOUTFS will then

be set to 16 • 2.5mA = 40mA.

OPERATION

Changing GAIN_ADJ to 0x1F (+31) will decrease the cur-

rent by 10.8% to 35.7mA. Changing GAIN_ADJ to 0x20

(–32) will increase the current by 14.3% to 45.7mA.

Note that GAIN_ADJ appears in the denominator of the

equation for IOUTFS, so the adjustment resolution varies

from 0.5% to 0.3% per step. The circuit shown in Figure

6 may be used to vary the full-scale output current beyond

the range of the GAIN_ADJ register.

DAC linearity and harmonic distortion may be degraded

when using full-scale currents other than 40mA. The

full-scale current must not exceed 60mA, and is recom-

mended to be at least 10mA.

Table 1. Power-On Reset and Power-Down SPI Registers

ADDRESS BIT

NAME

DESCRIPTION

0x01

SW_RST

Software Reset. Set SW_RST = 1 to restore all registers to their power-on reset state. SW_RST is automatically cleared

when CS returns high. All registers reset to 0x00, except address 0x08 which resets to 0x08.

DAC_PD

DAC Power Down. Set DAC_PD = 1 to power down the DAC and FSADJ bias circuits.

FULL_PD

Full Power Down. Set FULL_PD = 1 to power down all active circuits on the chip and reduce the supply current to less

than 100µA.

0x02

CK_PD

CKP/N Clock Receiver Power Down. CKP/N clock receiver is powered down when CK_PD = 1.

DCKO_DIS

DCKOP/N Output Disable. Set DCKO_DIS = 1 to power down the DCKO LVDS transmitter. For DCKO_DIS = 1, DCKOP/N

are high impedance.

0x03

DCKI_EN

DCKIP/N Clock Receiver Enable. Set DCKI_EN = 1 to enable the DCKI clock receiver.

0x04

DA_EN

DAC Data Port A LVDS Receiver Enable. Set DA_EN = 1 to enable port A (DAP/N) LVDS receivers. For DA_EN = 0,

port A LVDS receivers are powered down and port A data will be zeroes.

DB_EN

DAC Data Port B LVDS Receiver Enable. Set DB_EN = 1 to enable port B (DBP/N) LVDS receivers. For DB_EN = 0,

port B LVDS receivers are powered down and port B data will be zeroes.

Note: Registers 0x01 to 0x04 reset to 0x00 (default).

Figure 6. LTC2000 Full-Scale Adjust from 20mA to 60mA

REF

LTC2000

REFIO

1.25V

10k

2000 F06

500Ω

0V TO 2.5V

LTC2630-LM12

FSADJ

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