IX6610

R00A

PRELIMINARY

17

Figure 12

IX6610 Application Diagram

2

Theory of Operation

The IX6610 is a PWM logic signal interface IC used on the primary side of a transformer coupled IGBT gate driver.

2.1

Detailed Circuit Description

2.1.1

Digital Input Interface

The external MCU provides TTL level compatible input

signals INA and INB. These input signals are fed

through the Schmitt trigger buffers to control the

secondary side IGBT drivers. An input signal interlock

function is implemented to prevent the simultaneous

conduction of the secondary side High side and Low

side IGBT’s. Figure 4 shows the behavior of the

interlock function.

PGND1

PGND1

PGND1

V

DD

V

DD

PGND2

PGND2

PGND2

PGND2

V

DD

V

DD

Softstart Control

Output Power Select

Watchdog

Timer

Reset

Generator

POR

THSD

Oscillator

Clock

Select

Power Supply

Fault Logic

Output Fault

Logic

Internal

V

REF

OVLO

UVLO

Start-Up

Regulator

3.3V

LDO

Precision

Current

Generator

Soft-Start

Control

Dead Time

Generator

Channel A

Leading Edge Pulse

Channel A

Trailing Edge Pulse

Channel B

Leading Edge Pulse

Channel B

Trailing Edge Pulse

PGND2

PGND1

TRDCN

RCVAP

RCVAN

RCVBP

RCVBN

VIN

VAUX

TEST

V

DD

CB

TRBP

TRBN

CA

TRDCP

GND

MODE

FLT RST

RESET

CLK

FAULT1

FAULT2

RBIAS

INB

INA

TRAP

TRAN

PGND2

RST

EN2

vbg

vbg

+

-

V

IN

VP

VN

COM

VP

VN

COM

CHAN-A

CHAN-B

22

µF

22

µF

22

µF

22

µF

VP=15V

VP=15V

VN=-5V

VN=-5V

2

1

3

4

5

6

7

8

9

10

11

12

13

14

17

16

15

18

19

20

21

22

23

24

25

26

27

28

PGND1

0V

50

50

50

0V

50

50

50

V

DD

50

50

50

V

EE

V

DD

50

50

50

V

EE

CHAN-A

CHAN-B

From MCU

From MCU

From MCU

From MCU

To MCU

To MCU

From MCU

From MCU

7.77k

0.2nF

0.2nF

0.2nF

22

µF

to MCU power

22

µF

15V

CHAN-A

CHAN-B

22

µF