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Rev. 1.0
7
LOW Vcc DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
CE2
V
tCDR
tR
IL
VIL
DR
V > 2.0V
VCC
CE2
< 0.2v
AC TEST CONDITIONS
KEY TO SWITCHING WAVEFORMS
Input Pulse Levels
Vcc/0V
WAVEFORMS
INPUTS
OUTPUTS
Input Rise and Fall Times
5ns
MUST BE STEADY MUST BE STEADY
Input and Output Timing
Reference Level
0.5Vcc
Output Load
See FIGURE 1A
and 1B
MAY CHANGE
FROM H TO L
WILL BE CHANGE FROM H
TO L
MAY CHANGE
FROM L TO H
WILL BE CHANGE FROM L
TO H
DON’T CARE ANY
CHANGE
PERMITTED
CHANGE STATE
UNKNOWN
DOES NOT APPLY
CENTER LINE IS HIGH
IMPEDANCE OFF STATE
High Speed Super Low Power SRAM
8K-Word By 8 Bit
WS6264